Abstract: A semiconductor device includes a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. Transitions of the clock signal are output in the gated clock signal in response to a clock enable signal having an enable value and are disabled from being output in the gated clock signal in response to the clock enable signal having a disable value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to the disable value in response to a disable control and sets the clock enable signal to the enable value in response to a wakeup control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides the disable control to the first portion during an operation.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

Abstract: In certain aspects, a memory device includes an array of memory cells and a peripheral circuit coupled to the array of memory cells. At least one of the memory cells is set to one of 2N levels corresponding to a piece of N-bits data, where Nis an integer greater than 1. The peripheral circuit is configured to apply a first program voltage to a word line of the memory cells, perform a first verification of the word line of the memory cells at a last level of the 2N levels after applying the first program voltage, perform a first verify fail count (VFC) based on a result of the first verification and a first VFC criterion, apply a second program voltage greater than the first program voltage to the first word line of the memory cells after performing the first VFC, and perform a second VFC based on the result of the first verification and a second VFC criterion different from the first VFC criterion within a period of applying the second program voltage.

Abstract: The present disclosure is directed to methods and systems for analyzing integrated circuits. The method includes performing a first resistor capacitor (RC) extraction process on a power-receiving circuit and producing a first RC model. The method also includes scanning a netlist of a power distribution network, the power distribution network electrically connected to the power-receiving circuit. The method further includes determining a selection of circuit elements of the power distribution network based on a predetermined criteria. The method further includes performing a second RC extraction process on the selection of circuit elements and producing a second RC model. The method further includes performing a simulation process on the power-receiving circuit and the power distribution network using the first and second RC models.

Abstract: Disclosed is a memory device comprising: a memory cell array having a plurality of rows of memory cells; a plurality of word lines coupled to the plurality of rows of memory cells respectively; wherein the memory device is configured to perform programming operations on a target memory cell in the plurality of rows of memory cells, wherein during the programming operations: applying a programming voltage to a selected word line corresponding to a row where the target memory cell locates to program the target memory cell to a target programming state; applying a predetermined voltage to the selected word line to reduce voltage changes caused by capacitive coupling between an unselected word line adjacent to the selected word line and the selected word line; and applying a verification voltage to the selected word line to perform verification operations to verify whether a threshold voltage of the target memory cell is larger than a target threshold voltage corresponding to the target programming state based on

Abstract: A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a dielectric stack over a substrate, forming a functional layer and a semiconductor channel through the dielectric stack, forming a conductor/insulator stack based on the dielectric stack, and forming memory cells through the conductor/insulator stack. Each memory cell includes a portion of the functional layer and the semiconductor channel. At least one of the functional layer and the semiconductor channel includes a certain amount of deuterium elements.

Abstract: a memory device includes an array of memory cells. Each memory cell includes a vertical transistor having a semiconductor body vertically extending in a first direction. Each memory cell includes a storage unit coupled to a first end of the semiconductor body and a bit line extending in a second direction perpendicular to the first direction. The bit line is connected to second ends of the semiconductor bodies of a row of the vertical transistors. The bit line includes a semiconductor epitaxial layer extending in the second direction and connected to the second ends of the semiconductor bodies of the row of the vertical transistors at a top surface of the semiconductor epitaxial layer.

Abstract: A method of fabricating a semiconductor device can include providing a substrate, etching the substrate from a first side to form at least one vertical pillar having a first and a second end, forming at least one gate line on a gate dielectric layer formed on sidewalls of the at least one vertical pillar, forming a first p-type region at the first end of the at least one vertical pillar, forming a storage unit connecting the first p-type region, removing a portion of the substrate at a second side opposite to the first side of the substrate to expose the second end of the at least one vertical pillar, forming a second p-type region made of at least p-type SiGe at the second end of the at least one vertical pillar, and forming a bit line in connection with the second p-type region.

Abstract: In an aspect, a memory device comprises a memory configured to store a program code and a processor. The processor is configured to perform a first programming to a first cell of the memory device by incremental step pulse programming (ISPP) with a first step voltage. The processor is further configured to perform a second programming to a second cell of the memory device by ISPP with a second step voltage. The first step voltage is larger than the second step voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage. The first cell corresponds to a first target voltage and the second cell corresponds to a second target voltage.

Abstract: An operation method of a memory system includes sending, by a controller, a first scanning command to a memory and determining a valley voltage by scanning a plurality of memory cells. The valley voltage is determined according to a count of memory cells corresponding to different threshold voltages in a preset threshold voltage interval, the count of memory cells corresponding to the different threshold voltages being obtained by scanning the plurality of memory cells, the valley voltage being a threshold voltage corresponding to the minimum count of memory cells in the threshold voltage interval. The operation method includes sending, by the controller, a first read command to the memory, the first read command being used for instructing the memory to use the valley voltage as a reference read voltage to read target data. The operation method also includes reading, by the memory, the target data according to the valley voltage.

Abstract: Examples of the present disclosure provide a memory system and operation method thereof, a host device and operation method thereof, and a computer-readable storage medium. The memory system includes a memory device and a memory controller coupled to the memory device; The memory controller is configured to: receive a read command, the read command indicating to read event log information generated during running of firmware, the event log information including an index number and a parameter value of an event log; and the firmware runs different functional modules to correspondingly generate different event log elements, the different event log elements corresponding to different index numbers.

Abstract: The present disclosure involves methods, apparatuses, and computer-readable storage media for media scan in a memory system. In one example, a method for a memory system includes receiving commands from a host coupled to the memory system, wherein the memory system includes a memory device, the memory device includes a memory cell array, and the memory cell array includes a number of memory cells. The method further includes performing operations on the memory device based on the commands. The method further includes scanning at least a group of memory cells of the memory cell array by performing a number of scans within a scan period among the operations.

Abstract: The present disclosure provides a method for erasing a memory device. The method includes applying a word-line voltage to a word line of the memory device, wherein a first set of memory cells coupled to the word line are each configured to store a first number of bits data. The method also includes applying a hold voltage to a selected dummy line for a first time period, wherein a second set of memory cells coupled to the selected dummy line are each configured to store a second number of bits data less than the first number of bits data. The method further includes removing the hold voltage from the selected dummy line after the first time period such that an electric potential of the selected dummy line rises to a first voltage higher than the word-line voltage; and increasing the first time period incrementally in each of subsequent erase loops.

Abstract: An adapter cable can include a receptacle connector including contact pins as defined for a peripheral component interconnect express (PCIe) connector; edge connectors having edge pins as defined for a PCIe add-in card (AIC); and connections connecting the receptacle connector to the edge connectors, each connection connecting one of the contact pins to one of the edge pins.

Abstract: An operating method for a memory, a memory, and a memory system are provided in the present application. The memory includes at least a plurality of word lines and a plurality of strings, and the plurality of word lines include a target word line, and each word line is coupled to a plurality of strings. Each string includes a plurality of memory cells. In accordance with the operating method provided by the present application, the first verification and the second verification are performed on a plurality of target memory cells with first and second verify voltages during performing a first programming operation on a plurality of target memory cells in target string coupled to the target word line, and the second start program voltage is determined based on at least the second verification result, ensuring the accuracy of the second start program voltage.

Abstract: A method of operating a memory system can include maintaining one or more last write page table, the one or more last write page table is periodically updated to include at least one page serial number of the last page being written in a flash media, determining a last checkpoint in the flash media, the checkpoint is periodically updated and saved, determining the at least one page serial number in the one or more last write page table, validating a page having a highest page serial number in the one or more last write page table, validating pages having page serial numbers after the validated page having a page serial number in the one or more last write page table until an uncorrectable error correction code (UECC) occurs, and rebuilding mapping tables according to pages from the last checkpoint up to the last validated page before the UECC occurs.

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack over a substrate, wherein the alternating dielectric stack includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate. The method also includes forming a channel structure penetrating through the alternating dielectric stack and extending into the substrate, wherein the channel structure includes a channel layer disposed on a sidewall of a memory film. The method further includes removing the substrate and a portion of the memory film that extends into the substrate to expose a portion of the channel layer; and disposing an array common source (ACS) on the exposed portion of the channel layer.

Abstract: A method of programming a memory device. The memory device includes a plurality of memory strings, each memory string including a top transistor controlled by a top select gate (TSG) and connected to a bit line (BL), a bottom transistor controlled by a bottom select gate (BSG), and memory cells between the top and bottom transistors, each memory cell connected to a word line (WL). The method includes applying program pulses to a memory cell of the memory device in a program phase, verifying a voltage value of the memory cell in a verify phase, receiving a suspend command and performing a suspend operation, applying a discharge pulse to the memory cell in a discharge phase to thereby discharge the memory cell, wherein the discharge pulse includes a voltage pulse to an unselected top select gate (TSGunsel), and suspending programming or verifying of the memory cell in a suspend phase.

Abstract: The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer.