Abstract: A semiconductor device includes an active layer having a first side and a second side, a bit line layer having a first bit line sub-layer disposed on the first side and a second bit line sub-layer disposed on the second side, and capacitor structures. The active layer includes active units arranged in an array and disposed at intervals. The first and second bit line sub-layers are connected with the active units. The capacitor structures are disposed on the first side and the second side of the active layer and connected with the active units. By disposing the bit lines and the capacitor structures on two opposite sides of two ends of the active units, the semiconductor device can have larger spaces on the two sides of the ends of the active units to accommodate the capacitor structures, as compared with a semiconductor device with the same number of capacitor structures.

Abstract: Aspect of the disclosure provide a semiconductor device including a stack structure having a core region in which a plurality of channel structures are formed, and a semiconductor layer located on one side of the stack structure in a stacking direction of the stack structure, the channel structures extending to the semiconductor layer, and projections of the semiconductor layer and the channel structures in a plane parallel to the stacking direction not overlapping. The semiconductor device can further include a first insulating layer at least located on a first surface of the semiconductor layer far away from the stack structure, and a first leading-out portion penetrating through a portion of the first insulating layer corresponding to the core region in the stacking direction and being in contact with the semiconductor layer.

Abstract: A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.

Abstract: The disclosure provides a three-dimensional (3D) memory, a method of fabricating a 3D memory and a memory system. The 3D memory can include a stack including alternately stacked first dielectric layers and conductive layers, and a channel structure extending through the stack and including a second dielectric layer and a blocking layer disposed in this order from outside to inside. The second dielectric layer can have a dielectric constant greater than or equal to 3.9.

Abstract: A fabrication method of a semiconductor structure includes forming a stack structure and a memory channel structure on a substrate. The memory channel structure penetrates through the stack structure along a stack direction and extends into the substrate to form an extension part. The memory channel structure includes a memory function layer and a channel layer. The method further includes removing the substrate and exposing the extension part, and forming a sacrificial layer on a side of the stack structure where the substrate is removed from. The sacrificial layer wraps a part of the exposed extension part. The method also includes removing the memory function layer in the unwrapped extension part and exposing the corresponding channel layer, removing the sacrificial layer, exposing the remaining memory function layer in the extension part, and forming a semiconductor layer on a side of the stack structure where the sacrificial layer is removed from.

Abstract: The present disclosure provides page buffer circuits of 3D NAND devices. In some embodiments, the page buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment of a bit line, and a second bit line segment sensing branch connected to a second bit line segment of the bit line. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit. In some embodiments, the first bit line segment sensing branch comprises a first sense latch and a first bit line pre-charge path, and the second bit line segment sensing branch comprises a second sense latch and a second bit line pre-charge path.

Abstract: A structure for performing analysis includes a first opening formed on a back side of a substrate and passing through the substrate, a second opening connected with a bottom of the first opening and penetrating into a first dielectric layer formed on a front side of the substrate, a first conductive layer formed on a sidewall of the second opening and a contact element in the first dielectric layer, and a second conductive layer formed on a second dielectric layer. The first conductive layer contacts the second conductive layer electrically.

Abstract: A plurality of holes are formed extending vertically in a first dielectric deck that includes interleaved a plurality of first sacrificial layers and a plurality of first dielectric layers over a substrate. A plurality of sacrificial structures are formed in the holes. A second dielectric deck is formed having interleaved a plurality of second sacrificial layers and a plurality of second dielectric layers over the first dielectric deck. A slit opening is formed extending in the second dielectric deck, the slit opening aligned with and over the sacrificial source contact structures. The sacrificial structures are removed through the slit openings such that the slit opening is in contact with the holes to form a slit structure. A plurality of conductor layers are formed in the first and second dielectric decks through the slit structure, forming a memory stack. A source contact structure is formed in the slit structure.

Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate and a memory stack including interleaved conductive layers and dielectric layers on the substrate. The memory stack includes a core structure and a staircase structure. The staircase structure is on one side of the memory stack. The 3D memory device also includes a dummy channel structure extending vertically through the staircase structure. The dummy channel structure includes a plurality of sections along a vertical side of the dummy channel structure. The plurality of sections respectively interface with the interleaved conductive layers in the staircase structure. At least one of the plurality of sections includes a non-flat surface at an interface between the at least one of the plurality of sections and a corresponding conductive layer.

Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising memory cells coupled to a plurality of word lines and configured to store data, a row decoder configured to decode an address of a word line from the plurality of word lines, and a controller coupled to the array of memory cells. The controller includes a first multiplexer configured to receive a first plurality of trim selections, while each of the first plurality of trim selections is associated with a first trim parameter and each of the first plurality of trim selections corresponds to each of the plurality of word lines, respectively. The controller also includes a second multiplexer configured to receive a first plurality of trim settings, while each of the first plurality of trim settings corresponds to a value associated with the first trim parameter.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, a layer stack, memory cells, a semiconductor layer, a contact structure, and gate line slit structures. The substrate includes a doped region. The layer stack is formed over the substrate. The memory cells are formed through the layer stack over the substrate. The semiconductor layer is formed on the doped region and a side portion of a channel layer that extends through the layer stack. The contact structure electrically contacts the doped region. A dielectric material is filled in the gate line slit structures. Air gaps are formed in the gate line slit structures by the dielectric material.

Abstract: In certain aspects, a pattern generation system includes a pattern generator, a memory, a pin function register, a pin function mapper, and a set of source selectors. The pattern generator generates a plurality of source patterns. The memory stores a lookup table set. The lookup table set describes a mapping relationship between the plurality of source patterns and a set of test channels, and is indexed based on a pin function index. The pin function register stores a value of the pin function index. The pin function mapper executes a pin-mapping operation to generate a set of source selection signals based on the value of the pin function index and the lookup table set. Each source selector selects and outputs a source signal from the plurality of source patterns to a corresponding test channel based on a corresponding source selection signal received from the pin function mapper.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, core regions, isolation regions, a layer stack, channel structures, and an isolation structure. Each core region is surrounded by one or more of the isolation regions. The layer stack is formed in each core region and includes first dielectric layers and conductor layers that are alternatingly stacked over each other. The channel structures are formed through the layer stack. The isolation structure is formed in one or more of the isolation regions, and includes second dielectric layers and third dielectric layers that are alternatingly stacked over each other.

Abstract: A metal-dielectric bonding method includes providing a first semiconductor structure including a first semiconductor layer, a first dielectric layer on the first semiconductor layer, and a first metal layer on the first dielectric layer, where the first metal layer has a metal bonding surface facing away from the first semiconductor layer; planarizing the metal bonding surface; applying a plasma treatment on the metal bonding surface; providing a second semiconductor structure including a second semiconductor layer, and a second dielectric layer on the second semiconductor layer, where the second dielectric layer has a dielectric bonding surface facing away from the second semiconductor layer; planarizing the dielectric bonding surface; applying a plasma treatment on the dielectric bonding surface; and bonding the first semiconductor structure with the second semiconductor structure by bonding the metal bonding surface with the dielectric bonding surface.

Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method can comprise forming a film stack with a plurality of dielectric layer pairs on a substrate, forming a channel structure region in the film stack including a plurality of channel structures, and forming a first staircase structure in a first staircase region and a second staircase structure in a second staircase region. Each of the first staircase structure and the second staircase structure can include a plurality of division block structures arranged along a first direction. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.

Abstract: Implementations of the present disclosure provide a system includes a memory device for storing memory data. The memory device includes an array of memory cells and a plurality of word lines arranged in a plurality of rows and coupled to the array of memory cells. The system also includes a memory controller, having a processor and a memory, operatively coupled to the array of memory cells. The system further includes a host, having another processor and another memory, operatively coupled to the memory controller. The other processor of the host is configured to perform a first RAID encode operation on memory data to form first parity data. The processor of the memory controller is configured to receive the first parity data and the memory data, and perform a second RAID encode operation on the first parity data and the memory data to form second parity data.

Abstract: A method for operating a memory is provided, including, for example, obtaining a set of read voltages, each of which can include an initial voltage value and an offset voltage value with a certain offset relative to the initial voltage value. The initial voltage value in each of the set of read voltages can be a preset read voltage for distinguishing two adjacent memory states of memory cells of the memory. The operating method can further include performing read operations respectively based on the initial voltage values and the offset voltage values, obtaining the quantity of memory cells in which a read result corresponding to each voltage value meets set conditions, determining a difference between the two quantities corresponding to every two adjacent voltage values belonging to the same set of read voltages, and determining an optimal read voltage for distinguishing the two adjacent memory states based on the difference.

Abstract: In certain aspects, a memory system includes at least one memory device and a memory controller coupled to the at least one memory device. The memory controller may be configured to determine a current power consumption value indicating total concurrent power consumption of executing a plurality of memory operations in parallel. The memory controller may also be configured to determine an addon power consumption value indicating additional power consumption of executing a subsequent memory operation. The memory controller may be further configured to determine whether a summation of the current and the addon power consumption values exceeds a predetermined power consumption threshold. After determining that the summation of the current and the addon power consumption values does not exceed the predetermined power consumption threshold, the memory controller may be configured to execute the subsequent memory operation in parallel with the plurality of memory operations.

Abstract: A semiconductor device includes a clock gating circuit and a control circuit. The clock gating circuit outputs a gated clock signal based on a clock signal. Transitions of the clock signal are output in the gated clock signal in response to a clock enable signal having an enable value and are disabled from being output in the gated clock signal in response to the clock enable signal having a disable value. The control circuit includes a first portion that operates based on the clock signal. The first portion sets the clock enable signal to the disable value in response to a disable control and sets the clock enable signal to the enable value in response to a wakeup control. The control circuit includes a second portion that operates based on the gated clock signal. The second portion provides the disable control to the first portion during an operation.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.