Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack of conductive layers and insulating layers stacked alternatingly in a first direction. The stack of conductive layers and insulating layers has a first side and a second side in the first direction. The semiconductor device then includes a semiconductor layer at the first side of the stack of conductive layers and insulating layers, and a first isolation structure extending through, in the first direction, the semiconductor layer and a subset of the stack of conductive layers and insulating layers. The subset of the stack of conductive layers and insulating layers includes a first conductive layer. The first isolation structure separates a first portion of the first conductive layer from a second portion of the first conductive layer.

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Abstract: A memory device includes memory cells, and a first latch circuit, a second latch circuit, and a third latch circuit, coupled to the memory cells, wherein the first latch circuit is configured to store verification data during a verification operation, the second latch circuit is configured to store failure pattern data during the verification operation, and the third latch circuit is configured to store program data.

Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.

Abstract: Embodiments of methods to form three-dimensional (3D) memory devices include the following operations. First, an initial channel hole is formed in a stack structure of a plurality first layers and a plurality of second layers alternatingly arranged over a substrate. An offset is formed between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole. A semiconductor channel is formed by filling the channel hole with a channel-forming structure, the semiconductor channel having a memory layer including a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions.

Abstract: Embodiments of systems and methods for dicing a bonded structure are provided. A method for dicing a bonded structure includes thinning a top surface and a bottom surface of a bonded structure. The bonded structure may have a first wafer and a second wafer bonded with a bonding interface. The method may also include forming a series of ablation structures in the first wafer and the second wafer. The series of ablation structures may be between a first part and a second part of the bonded structure. The method may also include separating the first part and the second part of the bonded structure along the series of ablation structures.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure that includes alternating insulating layers and word line layers. The semiconductor device also includes a first channel structure extending through the stack structure, a first top select gate (TSG) layer over the stack structure, and a second TSG layer over the first TSG layer. The semiconductor device further includes a second channel structure extending through the first and second TSG layers, where the second channel structure is positioned over and coupled to the first channel structure.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor structure, a second semiconductor structure opposite to the first semiconductor structure, and an interface layer between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second semiconductor structure includes a plurality of peripheral circuits electrically connected to the memory stack. The interface layer includes single crystalline silicon and a plurality of interconnects between the memory stack and the peripheral circuits.

Abstract: The present disclosure provides buffer circuits of 3D NAND memory device. In some embodiments, the buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment and including a low-voltage latch, and a second bit line segment sensing branch connected to a second bit line segment and including a sensing latch. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.

Abstract: Aspects of the disclosure provide an interface between a host and a multi-plane flash memory. For example, the interface can include a first storage unit, a second storage unit and a controller. The first storage unit can be configured to receive and store a first plane pipeline command issued from the host, and output the first plane pipeline command to a first plane of the flash memory. The second storage unit can be configured to receive and store a second plane pipeline command issued from the host, and output the second plane pipeline command to a second plane of the flash memory. The controller can be electrically connected to the first storage unit and the second storage unit, and configured to output the first and second plane pipeline commands to the first and second planes, respectively, when no read process is performed on the first plane and the second plane.

Abstract: In certain aspects, a first opening extending vertically through a first dielectric deck including a first plurality of interleaved sacrificial layers and dielectric layers above a substrate is formed. A high-k dielectric layer and a channel sacrificial layer free of polysilicon are subsequently formed along a sidewall of the first opening. A second opening extending vertically through a second dielectric deck including a second plurality of interleaved sacrificial layers and dielectric layers on the first dielectric deck is formed to expose the channel sacrificial layer in the first opening. The channel sacrificial layer is removed in the first opening. A memory film and a semiconductor channel are subsequently formed over the high-k dielectric layer along sidewalls of the first and second openings.

Abstract: In certain aspects, a memory device includes a non-volatile memory storing firmware, a control logic coupled to the non-volatile memory, and an array of memory cells coupled to the control logic, the array of memory cells is embedded with instructions that are executable by the control logic. The control logic is configured to perform a power-on reset (POR) initialization operation to control an initialization of the memory device based on the firmware, repair the firmware based on execution of the instructions embedded on the array of memory cells, and perform a remaining POR initialization operation based on the repaired firmware.

Abstract: In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and I/O control logic coupled to the I/O circuit. The array of memory cells includes P groups of banks. P redundant banks are included in and shared by the P groups of banks. The I/O circuit is coupled to the P groups of banks and configured to direct P×N pieces of data to or from P×N working banks, respectively. The I/O control logic is configured to determine the P×N working banks from the P groups of banks based on bank fail information indicative of K failed main banks from the P groups of banks. The P×N working banks include K redundant banks of the P redundant banks. The I/O control logic is also configured to control the I/O circuit to direct P×N pieces of data to or from the P×N working banks, respectively.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

Abstract: A 3D-NAND memory device is provided. The memory device includes a substrate, a bottom select gate (BSG) disposed over the substrate, a plurality of word lines positioned over the BSG with a staircase configuration and a plurality of insulating layers disposed between the substrate, the BSG, and the plurality of word lines. In the disclosed memory device, one or more first dielectric trenches are formed in the BSG and extend in a length direction of the substrate to separate the BSG into a plurality of sub-BSGs. In addition, one or more common source regions are formed over the substrate and extend in the length direction of the substrate. The one or more common source regions further extend through the BSG, the plurality of word lines and the plurality of insulating layers.

Abstract: In certain aspects, a memory device includes a bit line, a plurality of memory cells coupled with the bit line, and N selectors, where N is a positive integer greater than 1, and N word lines. Each one of the plurality of memory cells includes N phase-change memory (PCM) elements. Each one of the N selectors is coupled with a respective one of the N PCM elements. Each one of the N word lines is coupled with a respective one of the N selectors.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are stacked over one another.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a memory stack of gate layers and insulating layers. The gate layers and the insulating layers are stacked alternatingly and are formed into stair steps in a staircase region. The semiconductor device includes a first landing pad on a first gate layer of a first stair step. The first gate layer is a top gate layer of the first stair step. The semiconductor device further includes a first sidewall isolation structure on a riser sidewall of a second gate layer of a second stair step. The second gate layer is a top gate layer of the second stair step and is stacked on the first gate layer in the memory stack. The first sidewall isolation structure isolates the second gate layer from the first landing pad.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes a stack structure of alternating insulating layers and word line layers, a first top select gate (TSG) layer over the stack structure, and a separation structure extending through the first TSG layer, where the first TSG layer is divided by the separation structure into a first sub TSG layer and a second sub TSG layer. The semiconductor device includes a conductive layer positioned between the first sub TSG layer and the separation structure, and between the second sub TSG layer and the separation structure.

Abstract: Methods for input/output voltage training of a three-dimensional (3D) memory device is disclosed. The method can comprise the following operations: (1) setting a reference voltage value at an on-die termination (ODT) enabled status; (2) controlling the 3D memory device to perform a write training process; (3) determining whether a further write training process is needed; (4) in response to determining that the further write training process is needed, repeating operations (1), (2) and (3); and (5) in response to determining that the further write training process is not needed, setting the reference voltage value as an optimized reference voltage value.