Abstract: In a TSC structure, a first dielectric layer is formed over a first main surface of a substrate. A TSC is formed in the first dielectric layer and the substrate so that the TSC passes through the first dielectric layer and extends into the substrate. A conductive plate is formed over the first dielectric layer and electrically coupled with the TSC. A second dielectric layer is formed on an opposing second main surface of the substrate. A first via is formed in the second dielectric layer, and a first end of the first via extends into the substrate to be in contact with the TSC. A second via is formed in the second dielectric layer and a first end of the second via extends into the substrate. A metal line is formed over the second dielectric layer so as to be coupled to the first via and the second via.

Abstract: First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a programmable logic device, an array of static random-access memory (SRAM) cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

Abstract: A peak power management (PPM) system is provided for managing peak power operations between two or more NAND memory dies. The PPM system includes a PPM circuit on each NAND memory die. Each PPM circuit includes a first pull-up driver electrically connected to a first power source and a first end of a PPM resistor; a second pull-up driver electrically connected to a second power source and a second end of the PPM resistor; a pull-down driver electrically connected to the second end of the PPM resistor; and a PPM contact pad connected to the second end of the PPM resistor. The PPM contact pads of the two or more NAND memory dies are electrically connected with each other with a common electric potential. The PPM system is configured to manage peak power operations according to the electric potential of the PPM contact pads.

Abstract: A method includes providing a structure including a carrier wafer, and a first device wafer with an adhesion layer between the carrier wafer and the first device wafer; and forming a plurality of first ablation structures in the structure, each of the plurality of first ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer. Each of the plurality of first ablation structures has a portion inside the carrier wafer with a depth no greater than one half of a thickness of the carrier wafer. The first device wafer includes a plurality of first dies, each pair of adjacent first dies being separated by one of the plurality of first ablation structures. The plurality of first ablation structures are formed by either laser grooving or mechanical sawing.

Abstract: Aspects of the disclosure provide a memory system, a semiconductor device and fabrication method for the semiconductor device. The semiconductor device includes a memory stack with gate layers and insulating layers, and the gate layers and the insulating layers are stacked alternatingly. The semiconductor device also includes a first channel structure formed in a first channel hole in the memory stack. The first channel structure includes a channel plug in connection with a channel layer of the first channel structure. The semiconductor device also includes an isolation stack including a landing liner layer and an isolation layer. A first portion of the landing liner layer is laid on the channel plug. The semiconductor device includes a first contact structure formed in the isolation stack. The first contact structure is connected to the channel plug via an opening in the first portion of the landing liner layer.

Abstract: The present disclosure provides a method of data protection for a NAND memory. The method can include programming a selected page of the NAND flash memory device according to programming data. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations, with ones of the plurality of verifying operations performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the programming data. The method can also include determining a completion of the programming of the selected page based on each of the plurality of verification operations returning a pass result. The method can also include performing, after the determining, a read operation on the selected page by the NAND flash memory device to self-verify data stored at the selected page according to the programming data.

Abstract: The present disclosure provides a method for debugging of flash memory devices using NAND self-verification The method can include programming a selected page of the NAND flash memory device according to first and second programming data. The selected page can include a plurality of memory cells corresponding to a word line. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations. Ones of the plurality of verifying operations can be performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the first or second programming data The method can also include performing self-verification on the selected page to determine whether data stored at the selected page was overwritten and generating a fail indication upon determining that the data stored at the selected page was overwritten.

Abstract: The present disclosure provides a method of data protection for a NAND memory. The method includes programming first and second pages of a NAND flash memory device according to programming data such that data stored in the first and second pages are redundant. The programming of the first and second pages includes a plurality of programming operations using a plurality of programming voltages and a plurality of verifying operations to determine whether programmed memory cells of the first page have threshold voltage levels according to the programming data. The method also includes determining a completion of the programming of the first and second pages based on each of the plurality of verification operations returning a pass result. The method also includes performing, after the determining, a read operation on the second page by the NAND flash memory device to self-verify the data stored at the second page.

Abstract: A phase-change memory (PCM) device includes a first electrode, a second electrode, a memory layer, and a heater. The memory layer includes a phase-change material and is electrically coupled between the first electrode and the second electrode. The heater is arranged near the memory layer and is configured to heat a programming region of the memory layer in response to an electric current that passes through the heater. The heater is coupled to a power source via an electric current path that does not pass through the memory layer.

Abstract: A memory device includes memory cells in rows, word lines respectively coupled to the rows, and a control circuitry coupled to the memory cells via the word lines. The control circuitry is configured to apply a first program voltage to a first word line of the word lines. The first word line is coupled to a first row of the memory cells. The control circuitry is also configured to, after applying the first program voltage to the first word line, apply a second program voltage to a second word line of the word lines. The second word line is coupled to a second row of the memory cells. The control circuitry is also configured to, after applying the second program voltage to the second word line, apply a first pre-charge voltage to the first word line and a second pre-charge voltage to the second word line. The second pre-charge voltage is greater than the first pre-charge voltage.

Abstract: Embodiments of three-dimensional (3D) memory devices having a memory layer that confines electron transportation and methods for forming the same are disclosed. A method for forming a 3D memory device includes the following operations. An initial channel hole is formed in a stack structure having a plurality of first layers and a plurality of second layers alternatingly arranged over a substrate. A portion of each one of the plurality of first layers facing a sidewall of the initial channel hole is removed to form a channel hole. A semiconductor channel structure is formed in the channel hole. The semiconductor channel structure includes a memory layer following a profile of a sidewall of the channel hole. The plurality of first layers are removed to form a plurality of tunnels. Portions of the memory layer are removed, through the tunnels, to divide the memory layer into a plurality of disconnected sub-memory portions.

Abstract: A memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of strings. A method of programming the memory device includes programming a first row of the memory cells. The method also includes, after programing the first row of the memory cells, programming a second row of the memory cells. The second row is adjacent to the first row in a first string direction. The method further includes, after programming the second row of the memory cells, programming a third row of the memory cells. The third row is two rows apart from the second row in a second string direction opposite to the first string direction.

Abstract: Embodiments of source structure of a three-dimensional (3D) memory device and method for forming the source structure of the 3D memory device are disclosed. In an example, a NAND memory device includes a substrate, an alternating conductor/dielectric stack, a NAND string, a source conductor layer, and a source contact. The alternating conductor/dielectric stack includes a plurality of conductor/dielectric pairs above the substrate. The NAND string extends vertically through the alternating conductor/dielectric stack. The source conductor layer is above the alternating conductor/dielectric stack and is in contact with an end of the NAND string. The source contact includes an end in contact with the source conductor layer. The NAND string is electrically connected to the source contact by the source conductor layer. In some embodiments, the source conductor layer includes one or more conduction regions each including one or more of a metal, a metal alloy, and a metal silicide.

Abstract: Memory device includes a bottom-select-gate (BSG) structure formed on a substrate. Cut slits are formed vertically through the BSG structure. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

Abstract: In an example of the present disclosure, 3D memory device includes a memory array structure and a staircase structure dividing the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs, and a bridge structure in contact with the first memory array structure and the second memory array structure. A stair of the plurality of stairs includes a conductor portion on a top surface of the stair and electrically connected to the bridge structure, and a dielectric portion at a same level and in contact with the conductor portion. The stair is electrically connected to at least one of the first memory array structure and the second memory array structure. The conductor portion includes a portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure.

Abstract: According to an aspect of the disclosure, a semiconductor device is provided. The semiconductor device includes one or more bottom select gate (BSG) layers positioned over a substrate, a plurality of word line layers positioned over the one or more BSG layers, and a plurality of insulating layers positioned on the substrate. The plurality of insulating layers is disposed on surfaces of the substrate, the one or more BSG layers, and the plurality of word line layers. The semiconductor device includes a first dielectric structure extending from the substrate and through the one or more BSG layers, and a second dielectric structure extending from the first dielectric structure and through the plurality of word line layers.

Abstract: A method for taping a wafer is disclosed. A wafer taping device comprising a wafer stage is provided. A wafer is mounted and secured on the wafer stage. A tape is delivered along a first direction over the wafer. The tape is forced into adhesion with a surface of the wafer in a non-contact manner. The tape is cut along a perimeter of the wafer.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a plurality of channel structures each extending vertically through the memory stack, a conductive layer in contact with source ends of the plurality of channel structures, a first source contact electrically connected to the channel structures, and a second source contact electrically connected to the channel structures.

Abstract: In certain aspects, a circuit includes a page buffer including a plurality of portions, a clock path coupled to the plurality of portions of the page buffer, and a clock level set module coupled to the page buffer. Each of the portions is configured to sequentially receive a clock signal, and sequentially return a clock return signal in response to receiving the corresponding clock signal. The clock path is configured to merge the plurality of clock return signals. The clock level set module is configured to set a start level of a first clock return signal of the plurality of clock return signals based on a number of cycles in a first clock signal of the plurality of clock signals. The first clock return signal corresponds to the first clock signal.

Abstract: Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A semiconductor device includes one or more units of strings of cells, and dielectric structures extending in a vertical direction and a first direction perpendicular to the vertical direction and separating adjacent units of strings of cells. Each unit of strings of cells includes a first string of cells each including first cells, and a second string of cells each including second cells.