Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes NAND memory cells and a first bonding layer including first bonding contacts. The semiconductor device also includes a second semiconductor structure including DRAM cells and a second bonding layer including second bonding contacts. The semiconductor device also includes a third semiconductor structure including a processor, SRAM cells, and a third bonding layer including third bonding contacts. The semiconductor device further includes a first bonding interface between the first and third bonding layers, and a second bonding interface between the second and third bonding layers. The first bonding contacts are in contact with a first set of the third bonding contacts at the first bonding interface. The second bonding contacts are in contact with a second set of the third bonding contacts at the second bonding interface. The first and second bonding interfaces are in a same plane.

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes a plurality of stairs. At least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

Abstract: A method for fabricating a substrate structure for packaging includes providing a core substrate, a plurality of conductive pads at a first surface of the core substrate, and a metal layer at a second surface of the core substrate opposite to the first surface; forming a conductive structure, for pasting the substrate structure onto an external component, on each of the plurality of conductive pads; forming a molding compound on the first surface of the core substrate and to encapsulate the conductive structure; and forming a plurality of packaging pads by patterning the metal layer at the second surface of the core substrate.

Abstract: Magnetic memory structure and memory device are provided. A magnetic memory structure includes a metal layer, a first magnetic tunnel junction, and a second magnetic tunnel junction. The metal layer includes a first contact region and a second contact region. Electrical resistivity of at least a first part of the first contact region is different than electrical resistivity of the second contact region. The first magnetic tunnel junction is disposed on the metal layer. The first magnetic tunnel junction includes a first free layer in contact with the first contact region of the metal layer. The second magnetic tunnel junction is disposed on the metal layer. The second magnetic tunnel junction includes a second free layer in contact with the second contact region of the metal layer.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending through the memory stack, and a through array contact (TAC) extending through the memory stack. Edges of the conductive layers along a sidewall of the TAC are recessed. The TAC includes a conductor layer and a spacer over the sidewall of the TAC.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a first die. The first die includes a semiconductor substrate with transistors formed on a first side of the semiconductor substrate. Further, the first die includes a connection structure extending through the semiconductor substrate and conductively connecting a first conductive layer disposed on the first side of the semiconductor substrate with a second conductive layer disposed on a second side of the semiconductor substrate that is opposite to the first side of the semiconductor substrate. Further, the first die includes a shielding structure disposed in the semiconductor substrate and between the connection structure and at least a transistor. The shielding structure includes a third conductive layer and can alleviate coupling between the connection structure and the transistor.

Abstract: A chip package structure includes a chip stack and a redistribution layer. The chip stack includes multiple chips stacked together, a molding layer encapsulating the multiple chips, and a vertical conductive element extending from a surface of the molding layer reach and coupled to the bonding pad. Each of the multiple chips includes a bonding pad not covered by the multiple chips. The redistribution layer is above the molding layer and includes a conductive layer coupled to the vertical conductive element, and an insulating layer over and partially exposing the conductive layer.

Abstract: A semiconductor device includes a first substrate, a second substrate, a first connection structure, and a second connection structure. A transistor is formed in a first side of the first substrate. A doped region is formed in a first side of the second substrate. The first connection structure is formed over a second side of the second substrate, and coupled to the doped region through a first VIA that extends from the second side of the second substrate to the doped region. The second connection structure is formed over the first side of the first substrate, connected with the first connection structure via a through silicon VIA, and coupled to the transistor through a bonding VIA. The first substrate is bonded to the second substrate by the bonding VIA, with the first side of the first substrate and the first side of the second substrate being facing each other.

Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method includes disposing an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate; and forming a staircase structure and a dividing wall in the alternating dielectric stack. The staircase structure and the dividing wall extend in a second direction parallel to the substrate, and the dividing wall is adjacent to the staircase structure. The method also includes forming, sequentially on the staircase structure, a first barrier layer and a second barrier layer different from the first barrier layer. The method further includes forming a gate line slit (GLS) opening in the dividing wall. The GLS opening penetrates through the alternating dielectric stack in the first direction and is distant from the second barrier layer in a third direction that is parallel to the substrate and is perpendicular to the second direction.

Abstract: A method for conducting a read-verification operation on a target memory cell in a three-dimensional (3D) memory device includes removing fast charges of the target memory cell at a read-prepare step and measuring a threshold voltage of the target memory cell at a sensing step. Removing the fast charges of the target memory cell includes applying a prepare voltage (Vprepare) on an unselected top select gate (Unsel_TSG) of an unselected memory string, applying a first off voltage (Voff) on a selected word line (Sel_WL) associated with the target memory cell, and applying a pass voltage (Vpass) on an unselected word line (Unsel_WL).

Abstract: Aspects of the disclosure provide methods for determining wafer flatness and for fabricating a semiconductor device. The method includes storing a first wafer expansion of a first wafer that is collected along a first direction parallel to a working surface of the first wafer during a lithography process. The lithography process is for patterning structures on the working surface of the first wafer. Before a fabrication step with a wafer flatness requirement, a wafer flatness of the first wafer is determined based on the first wafer expansion collected during the lithography process using a flatness prediction model that is configured to predict the wafer flatness. In an example, a layer is deposited on a back side of the first wafer with a thickness that is based on the determined wafer flatness of the first wafer.

Abstract: The present disclosure is directed to a memory structure including a staircase structure. The staircase structure can include a bottom select gate, a plate line formed above the bottom select gate, and a word line formed above the plate line. The pillar can extend through the bottom select gate, the plate line, and the word line. The memory structure can also include a source structure formed under the pillar and a drain cap formed above the pillar. The memory structure can further include a bit line formed above the drain cap.

Abstract: A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, a bottom select gate, and a P-well. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the P-well, apply a verifying voltage to a selected word line of the word lines after applying the erasing voltage to the P-well, and apply a first turn-on voltage to the bottom select gate, starting after applying the erasing voltage to the P-well and before applying the verifying voltage to the selected word line.

Abstract: A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level.

Abstract: A memory system includes a memory cell array and a controller coupled to the memory cell array. The controller is configured to control applying a first program voltage to a word line to program memory cells in the memory cell array, the memory cells being coupled to the word line, and in response to receiving a suspend command, control applying a positive bias discharge voltage to the word line when the first program voltage ramps down.

Abstract: Methods of peak power management (PPM) for a storage system having multiple memory dies are disclosed. Each memory die includes a first PPM circuit and a second PPM circuit. First PPM circuits of the multiple memory dies are electrically connected to form a first PPM group. Similarly, second PPM circuits are electrically connected to form a second PPM group. Peak power operations can be managed by switching on a first pull-down driver of the first PPM circuit on a selected memory die when a first PPM enablement signal of the first PPM group is zero; waiting for a first delay period; switching on a second pull-down driver of the second PPM circuit on the selected memory die when a second PPM enablement signal of the second PPM group is zero. The first and second PPM enablement signals depend on the current flowing through each pull-down driver in the first and second PPM groups.

Abstract: In certain aspects, a method for training a model is disclosed. A model for measuring a geometric attribute of a hole structure in a semiconductor chip is provided by at least one processor. A plurality of training samples each including a pair of an optical spectrum signal and a reference signal corresponding to a same hole structure are obtained by the at least one processor. The reference signal is labeled with a labeled geometric attribute of the hole structure. An estimated geometric attribute of the hole structure is estimated using the model. A parameter of the model is adjusted based, at least in part, on a difference between the labeled geometric attribute and the estimated geometric attribute in each of the training samples by the at least one processor.

Abstract: Aspects of the disclosure provide a semiconductor device and a method to manufacture the semiconductor device. A channel hole is formed in a stack including alternating first layers and second layers. The stack is formed over a substrate of the semiconductor device. A gate dielectric layer and a channel layer are sequentially formed in the channel hole. Laser annealing is performed on the channel layer using laser light. An incidence angle of the laser light on an upper surface of the channel layer causes a total internal reflection to occur at an interface between the channel layer and the gate dielectric layer and an interface between the channel layer and an insulating layer that is adjacent to the channel layer.

Abstract: The present disclosure is directed to methods and systems for analyzing integrated circuits. The method includes performing a first resistor capacitor (RC) extraction process on a power-receiving circuit and producing a first RC model. The method also includes scanning a netlist of a power distribution network, the power distribution network electrically connected to the power-receiving circuit. The method further includes determining a selection of circuit elements of the power distribution network based on a predetermined criteria. The method further includes performing a second RC extraction process on the selection of circuit elements and producing a second RC model. The method further includes performing a simulation process on the power-receiving circuit and the power distribution network using the first and second RC models.

Abstract: A three-dimensional (3D) memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second sets of memory layers. The 3D memory device may further include a peripheral circuit that includes a word line (WL) driving circuit configured to when programming a first memory layer of the first set of memory layers, apply a first pre-charge voltage to the first dummy memory layer during a pre-charge period associated with the first memory layer, and when programming a second memory layer of the first set of memory layers located above the first memory layer, apply a second pre-charge voltage to the first dummy memory layer during a pre-charge period associated with the second memory layer. The first pre-charge voltage may be larger than the second pre-charge voltage.