Abstract: A memory device may include a first set of word lines in a first zone and a second set of word lines in a second zone. When programming memory cells coupled to a first target word line of the first set of word lines, a first pass voltage may be applied to at least one word line of the first set of word lines. When programming memory cells coupled to a second target word line of the second set of word lines, a second pass voltage may be applied to at least one word line of the second set of word lines. The at least one word line of the first set of word lines and the at least one word line of the second set of word lines have been programmed. The second pass voltage may be higher than the first pass voltage.

Abstract: A semiconductor device semiconductor device includes a stack having a first surface and a second surface opposing the first surface. The stack can include word line layers and insulating layers alternating with the word line layers between the first surface and the second surface. The stack can further include a process stop layer between the lower most insulating layer and the second surface. The stack can extend along an X-Y plane having an X direction and a Y direction perpendicular. The semiconductor device can further include a slit structure crossing the stack between the first surface and the second surface in Z direction. In a cross-section perpendicular to the Y direction, distances between the slit structure and the process stop layer at two sides of the slit structure are each larger than distances at either side of the slit structure between the word line layers and the slit structure.

Abstract: A method for forming a three-dimensional memory device can include forming a staircase structure. An alternating layer stack is disposed and etched to form steps. A continuous layer disposed on the staircase structure continuously extends over the steps. An insulating layer is disposed on the continuous layer and a slit is formed extending through the staircase structure. The slit exposes sidewalls of the continuous layer and the steps. The sacrificial layer is removed and a cavity is formed in place of the continuous layer. An etch stop layer is disposed in the cavity and continuously extends over the steps. Openings are formed through the insulating layer and expose a portion of a lateral surface of the etch stop layer. The openings are extended through the etch stop layer to expose a lateral surface of each step of the steps. Contacts are formed in the openings.

Abstract: Aspects of the disclosure provide a method to manufacture a semiconductor device. The method includes filling a sacrificial layer in a first via of a first stack. An initial top CD is larger than an initial bottom CD of the first via. A second stack is formed along a vertical direction over the first stack. A third stack is formed along the vertical direction over the second stack. The first stack, the second stack, and the third stack include alternating insulating layers and gate layers. The insulating layers of the second stack etch at a faster rate than the insulating layers of the third stack and the gate layers of the second stack etch at a faster rate than the gate layers of the third stack. A first via, a second via, and a third via are formed in the first stack, the second stack, and the third stack, respectively.

Abstract: A three-dimensional (3D) memory device is disclosed. The 3D memory device comprises an alternating layer stack on a substrate, and a top selective gate cut structure having a laminated structure embedded in an upper portion of the alternating layer stack and extending along a lateral direction. The laminated structure of the top selective gate cut structure comprises a dielectric filling wall and a dummy channel and a dummy functional layer on both sides of the dielectric filling wall.

Abstract: A 3D memory device includes a memory stack including a memory block. The memory block includes a first memory array structure, a staircase structure, a second memory array structure in a first lateral direction, and a plurality of strings in a second lateral direction. The staircase structure includes a staircase zone and a bridge structure adjacent to the staircase zone. The 3D memory device also includes a SSG cut structure. The SSG cut structure includes a first portion between a first string and a second string and extends in the bridge structure in the first lateral direction. The staircase zone includes a first staircase conductively connected to first memory cells in the first string through the bridge structure and a second staircase conductively connected to second memory cells in the second string in the first memory array structure through the bridge structure.

Abstract: A semiconductor device includes a bit line unit, a word line unit, a bit line drive unit, and a word line drive unit. The bit line unit is configured to divide the word line unit into a first word line unit and a second word line unit. The distance between the second word line unit and the word line drive unit is greater than that the distance between the first word line unit and the word line drive unit. The word line drive unit is configured to provide the driving voltage for programming to the word line unit. The bit line drive unit is configured to apply the first bias voltage to the bit line unit that performs the dividing to obtain the first word line unit in the charging phase of programming, and to apply the second bias voltage to the bit line unit that performs the dividing to obtain the second word line unit in the discharging phase of programming.

Abstract: The present application discloses a memory device, a programming method and a memory system. The memory device comprises: a memory cell array comprising a plurality of word lines and a plurality of bit lines; each of the word lines comprising at least two word line segments; each of the word line segment in the word line having different signal transmission distances from a word line driver; different word line segments in the word line corresponding to different bit lines respectively; the word line driver configured to apply a word line voltage to the word line; a bit line driver configured to apply different bias voltages to different bit lines corresponding to the different word line segments respectively during application of a programming pulse.

Abstract: Methods for polishing dielectric layers using an auto-stop slurry in forming semiconductor devices, such as three-dimensional (3D) memory devices, are provided. The methods include forming a stack structure in a staircase region and a core array region, the stack structure including a staircase structure in the staircase region; forming a dielectric layer over the staircase region and a peripheral region outside the stack structure; and polishing the dielectric layer using an auto-stop slurry containing a ceria-based abrasive.

Abstract: In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and control logic coupled to the I/O circuit. The array of memory cells includes a plurality of banks including a plurality of main banks and a redundant bank. The I/O circuit is coupled to each pair of adjacent banks of the plurality of banks and configured to direct a piece of data to or from either bank of each pair of adjacent banks. The control circuit is configured to select one bank of each pair of adjacent banks based on bank fail information indicative of a failed main bank of the plurality of main banks. The control circuit is further configured to control the I/O circuit to direct the piece of data to or from the selected bank of each pair of adjacent banks.

Abstract: Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to, in response to a block of the plurality of blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.

Abstract: The disclosure provides an erase method for a memory device. In the method, during a time period, a first positive voltage is applied to a body portion of a memory cell string of the memory device. The memory cell string includes memory cell transistors and select transistors connected in series. A second positive voltage is applied to a bit line signal of the memory cell string. A third positive voltage is applied to a first top select gate signal to turn on a first top select transistor of the select transistors so that the memory cell transistors are coupled to the bit line signal through the first top select transistor. A ground level voltage or a fourth positive voltage is applied to a word line signal of the memory cell transistors. Both the third and fourth positive voltages are less than the second positive voltage.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate. The connection region is arranged between the first and second array regions and the first staircase has non-quadrilateral treads. A second staircase is formed in the connection region of the stack over the substrate and the second staircase has non-quadrilateral treads. The connection region in the stack includes a separation region between the first and second staircases.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

Abstract: The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.

Abstract: A non-volatile memory device includes a plurality of word lines and a control circuit. The control circuit is configured to apply a first word line pre-pulse signal of a plurality of word line pre-pulse signals to a first group of the plurality of word lines, apply a second word line pre-pulse signal of the plurality of word line pre-pulse signals to a second group of the plurality of word lines during a pre-charge period, and apply a third word line pre-pulse signal of the plurality of word lines pre-pulse signals to a third group of the plurality of word lines during the pre-charge period. A voltage level of the second word line pre-pulse signal is greater than that of the first word line pre-pulse signal, and a voltage level of the third word line pre-pulse signal is greater than that of the second word line pre-pulse signal.

Abstract: First semiconductor structures are formed on a first wafer. At least one of the first semiconductor structures includes a processor, an array of SRAM cells, and a first bonding layer including first bonding contacts. Second semiconductor structures are formed on a second wafer. At least one of the second semiconductor structures includes an array of NAND memory cells and a second bonding layer including second bonding contacts. The first wafer and the second wafer are bonded in a face-to-face manner, such that the at least one of the first semiconductor structures is bonded to the at least one of the second semiconductor structures. The first bonding contacts of the first semiconductor structure are in contact with the second bonding contacts of the second semiconductor structure at a bonding interface. The bonded first and second wafers are diced into dies. At least one of the dies includes the bonded first and second semiconductor structures.

Abstract: Aspects of the disclosure provide a semiconductor device. The semiconductor device includes a stack structure and a contact structure. The stack structure comprises interleaved gate layers and insulating layers. The contact structure comprises a conductive structure and one or more insulating structures. The conductive structure can extend through the stack structure and form a conductive connection with one of the gate layers. The one or more insulating structures surround the conductive structure and electrically isolate the conductive structure from remaining ones of the gate layers. The one or more insulating structures further include one or more first insulating structures. Each of the one or more first insulating structures is disposed between an adjacent pair of the insulating layers, and the one or more first insulating structures are disposed on a first side of the one of the gate layers.

Abstract: A memory device, a memory system, and a method thereof are provided. In the method, an N-th programming pulse is applied to a word line coupled to memory cells of the memory device each with a target programming state being an i-th programming state. A first sub-verification and an M-th second sub-verification are performed on the memory cells to obtain a first sub-result and an M-th second sub-result, respectively. Based on the M-th second sub-result, a subset of the memory cells is determined to be programmed with an (N+1)-th programming pulse. Then, the (N+1)-th programming pulse is applied to the word line. After applying the (N+1)-th programming pulse to the word line, the memory cells are determined to be successfully programmed to the i-th programming state based on the first sub-result indicating that a number of failed bits in the first sub-verification is less than a first preset value.