Abstract: A memory device comprising multiple memory planes is disclosed. The memory device further comprises a first pump set coupled with the multiple memory planes, and configured to supply a first output voltage to multiple linear regulators during a steady phase, and a second pump set coupled with the multiple memory planes, and configured to supply a second output voltage to the multiple linear regulators during a ramping phase. The multiple linear regulators can includes a first linear regulator set configured to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first group of word lines of the plurality of memory planes, and a second linear regulator set configured to regulate the first output voltage or the second output voltage to generate a second voltage bias for a second group of word lines of the plurality of memory planes.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, a channel structure, a channel local contact, a slit structure, and a staircase local contact. The memory stack includes interleaved conductive layers and dielectric layers above the substrate. The channel structure extends vertically through the memory stack. The channel local contact is above and in contact with the channel structure. The slit structure extends vertically through the memory stack. The staircase local contact is above and in contact with one of the conductive layers at a staircase structure on an edge of the memory stack. Upper ends of the channel local contact, the slit structure, and the staircase local contact are flush with one another.

Abstract: In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: Systems, methods and media of optimization of temporary read errors (TRE) in three-dimensional (3D) NAND memory devices are disclosed. A disclosed memory device can comprises a plurality of memory cells arranged as an array of NAND memory strings, a plurality of word lines couple to the memory cells, and a controller. The controller is configured to determine whether a next read operation is a first read operation of the memory device after recovering from an idle state, and In response to a positive result of the determination, control the memory device to perform an extended pre-phase of the first read operation before a read-phase of the first read operation.

Abstract: A method of cache programming of a NAND flash memory in a triple-level-cell (TLC) mode is provided. The method includes discarding an upper page of a first programming data from a first set of data latches in a plurality of page buffers when a first group of logic states are programmed and verified. The plurality of page buffers include the first, second and third sets of data latches, configured to store the upper page, middle page and lower page of programming data, respectively. The method also includes uploading a lower page of second programming data to a set of cache latches, transferring the lower page of the second programming data from the set of cache latches to the third set of data latches after discarding the lower page of the first programming data, and uploading a middle page of the second programming data to the set of cache latches.

Abstract: Aspects of the disclosure provide a method of preparing a focused ion beam (FIB) sample and analyzing the sample in an electron microscope system. The method can include forming, over a substrate, a target film having a thickness of less than a threshold corresponding to a limit for FIB requirements, and forming a supporting film over the target film. The method can also include obtaining a FIB sample that includes a portion of the target film and a portion of the supporting film and. The method can further include analyzing the obtained portion of the target film in an electron microscope system.

Abstract: A data operation method of a memory system is provided. The method includes, based on an obtained logical to physical mapping table, determining whether address values of a plurality of target physical addresses in the logical to physical mapping table corresponding to a plurality of target logical addresses are continuous; if so, selecting one of the plurality of target physical addresses as a base physical address, and setting a base physical address offset based on address values of remaining target physical addresses; and storing the base physical address and the base physical address offset into a cache of a memory controller, as a mapping relationship of the plurality of target logical addresses corresponding to the plurality of target physical addresses.

Abstract: The present disclosure provides a content addressable memory (CAM) for repairing firmware of multi-plane read operations in a flash memory device. The CAM comprises a set of CAM registers configured to store a mapping table. The mapping table comprises a plurality of old addresses, each old address corresponding to a new address. The CAM also comprises N comparators coupling to the set of CAM registers, and configured to compare the old addresses with N input signals for performing the multi-plane read operations on N memory planes, wherein N is an integer greater than 1. The CAM further comprises N multiplexers coupling to the N comparators respectively and to the set of CAM registers, and configured to generate N output signals for the multi-plane read operations. At least one of the N output signals comprises the new address according to the mapping table and a comparison output by the comparators.

Abstract: In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.

Abstract: In a method for manufacturing a semiconductor device, a doped region is formed in a substrate from a first main surface. An insulating layer is formed over the doped region of the substrate. Contacts are formed in the insulating layer such that the contacts extend into the doped region. A portion of the substrate is removed from a second main surface. A trench, a first conductive line, and a second conductive line are formed from the doped region of the substrate through etching the substrate from the second main surface. The trench extends through the substrate to expose the insulating layer. The first and second conductive lines are spaced apart from each other by the trench. The contacts are positioned along and in contact with the first and second conductive lines. The trench is filled with a dielectric material.

Abstract: Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.

Abstract: A method for programming a three-dimensional (3D) memory device is provided. The 3D memory device has a plurality of memory strings with memory cells vertically stacked, and each memory cell is addressable through a word line and a bit line. The method for programming the 3D memory device includes the following steps: applying a program voltage on a selected word line; applying a first pass voltage on a first group of unselected word lines; and applying a second pass voltage on a second group of unselected word lines, wherein the second pass voltage is different from the first pass voltage.

Abstract: The present disclosure provides a method of data protection for a NAND memory. The method can include programming a selected page of the NAND flash memory device according to programming data. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations, with ones of the plurality of verifying operations performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the programming data. The method can also include determining a completion of the programming of the selected page based on each of the plurality of verification operations returning a pass result. The method can also include performing, after the determining, a read operation on the selected page by the NAND flash memory device to self-verify data stored at the selected page according to the programming data.

Abstract: The present disclosure provides a method for debugging of flash memory devices using NAND self-verification The method can include programming a selected page of the NAND flash memory device according to first and second programming data. The selected page can include a plurality of memory cells corresponding to a word line. The programming of the selected page can include a plurality of programming operations and a plurality of verifying operations. Ones of the plurality of verifying operations can be performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the selected page have threshold voltage levels according to the first or second programming data. The method can also include performing self-verification on the selected page to determine whether data stored at the selected page was overwritten and generating a fail indication upon determining that the data stored at the selected page was overwritten.

Abstract: Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first bonding layer having a plurality of first bonding contacts, and a first via structure extending vertically through the first bonding layer and into the first semiconductor structure. The second semiconductor structure includes a second bonding layer having a plurality of second bonding contacts, and a second via structure extending vertically through the second bonding layer and into the second semiconductor structure. The first bonding contacts are in contact with the second bonding contacts at the bonding interface, the first via structure is in contact with the second via structure, and sidewalls of the first via structure and the second via structures have a staggered profile at the bonding interface.

Abstract: A method of peak power management (PPM) is provided for two NAND memory dies. each NAND memory die comprises a PPM circuit having a PPM contact pad held at an electric potential common between the two NAND memory dies. The method includes the following steps: detecting the electric potential during a first peak power check (PPC) routine for the first NAND memory die; driving the electric potential to a second voltage level if the detected electric potential is at a first voltage level higher than the second voltage level; generating a pausing signal in the electric potential to pause a second PPC routine for the second NAND memory die if no pausing signal is detected; and generating a resuming signal in the electric potential to resume the second PPC routine for the second NAND memory die after the first NAND memory die completes a first peak power operation.

Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method for forming a hole structure having a first hole portion and a second hole portion connected to and over the first portion in a stack structure of a semiconductor device includes determining a hard mask layer. An etching resistivity of the hard mask layer may be inversely proportional to a difference between a first lateral dimension of the first hole portion and a second lateral dimension of the second hole portion, and the first lateral dimension may be less than the second lateral dimension. The method may also include forming the hard mask layer over the stack structure, and patterning the hard mask layer to form a first patterned hard mask layer that has a first mask opening. The first mask opening may have the first lateral dimension.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A channel hole extending vertically above a substrate and having a plum blossom shape in a plan view is formed. A continuous blocking layer, a continuous charge trapping layer, and a continuous tunneling layer each following the plum blossom shape are formed from outside to inside in this order along sidewalls of the channel hole. A plurality of separate semiconductor channels each disposed over part of the continuous tunneling layer at a respective apex of the plum blossom shape are formed.

Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact and a first bonding alignment mark is formed above the first device layer. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact and a second bonding alignment mark is formed above the second device layer. The first bonding alignment mark is aligned with the second bonding alignment mark, such that the first bonding contact is aligned with the second bonding contact. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact at a bonding interface, and the first bonding alignment mark is in contact with the second bonding alignment mark at the bonding interface.