Patents Assigned to Zaidan Hojin Handotai Kenkyu Shinkokai
  • Patent number: 4338618
    Abstract: A composite junction-gate static induction transistor comprising a main static induction transistor (SIT) having a source, a gate and a drain, and an auxiliary static induction transistor having an auxiliary source connected to the source of the main SIT, an auxiliary gate connected to the gate of same SIT and an auxiliary drain connected to the auxiliary gate. An input signal current is applied to the composite gate and charges it up to a certain level, and thereafter it may flow through the auxiliary static induction transistor. Therefore, minority carrier storage in the junction-gate static induction transistor can be greatly reduced.
    Type: Grant
    Filed: November 1, 1979
    Date of Patent: July 6, 1982
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4334235
    Abstract: In an insulated-gate type static induction transistor having a source region for supplying charge carriers, a channel region through which said carriers travel, an insulated electrode type gate structure to which is inputted a gate voltage for controlling the travel of those carriers. A sharp build-up and non-saturating current vs. voltage characteristic, a high transconductance, and a small inter-electrode capacitance for high-speed operation are achieved by either reducing the channel length, or by reducing the depth of the source region smaller than that of the drain region, or by forming adjacent to the source region a blocking region of high impurity concentration relative to the channel region, or by arranging the effective channel close to the insulated gate.
    Type: Grant
    Filed: March 14, 1979
    Date of Patent: June 8, 1982
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4331737
    Abstract: The oxynitride film according to the present invention contains Ga and/or Al and has O/N ratio of at least 0.15. This film is obtained by relying on, for example, chemical vapor deposition technique. The O/N ratio in the film may be varied by, for example, varying the distance between the substrate and the substance-supply source, or by varying the proportion of an oxidizing gas contained in a carrier gas. This film is used either as a surface passivation film of III-V compound semiconductors such as GaAs, or as an insulating film for active surface portions of IG-FET, or as an optical anti-reflective film.
    Type: Grant
    Filed: December 11, 1980
    Date of Patent: May 25, 1982
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Ikuo Shiota
  • Patent number: 4329625
    Abstract: A light-responsive light-emitting diode display comprises a light-emitting diode circuit including a series connection of light-emitting diodes and a light-responsive current-controlling circuit connected in series to said light-emitting diode circuit for supplying a current thereto in correspondence with the ambient brightness. A unipolar photo-transistor can provide a current above a predetermined minimum value and increasing with the intensity of incident lights and can absorb excess voltages when applied. Light-responsive current-control reduces the useless power dissipation, and all solid-state display provides a very long service life.
    Type: Grant
    Filed: July 17, 1979
    Date of Patent: May 11, 1982
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Yasuo Okuno, Keishiro Takahashi
  • Patent number: 4317127
    Abstract: A static induction type semiconductor device containing a normal type static induction transistor having the structure that a source region, gate regions and drain regions are arrayed in a main surface of a channel-constituting semiconductor region, and that a sub-drain region is formed in the opposite surface of the channel-constituting semiconductor region so as to extend from a position corresponding to the source region up to a position corresponding to the drain regions. The provision of this sub-drain region makes it possible to realize easy isolation of a normal vertical structure static induction transistor in a semiconductor wafer, the normal vertical structure contributing to increasing the transconductance, and to improving the speed of operation, without sacrificing a high packing density.
    Type: Grant
    Filed: September 17, 1979
    Date of Patent: February 23, 1982
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4315796
    Abstract: A compound semiconductor mixed crystal is grown by causing semiconductor-constituent material to travel, in dissolved liquid phase, through a solution having a portion contacting the source material and held at a constant high temperature and another portion wherein growth of the mixed crystal takes place and held at a constant low temperature, while externally applying onto the surface of said solution vapor pressures of the material-constituting separately generated volatile elements. The vapor pressures of such volatile elements applied to the solution are determined by the measurement, as a function, of at least one physical property of the mixed crystal thus produced. Optimum vapor pressures of these elements may be effectively determined by successively growing, under the same conditions, two layers forming a light-emitting diode and by measuring the luminance of this diode.
    Type: Grant
    Filed: May 31, 1979
    Date of Patent: February 16, 1982
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4300151
    Abstract: A plurality of static induction transistors capable of establishing a controllable potential barrier for charge carriers in the channel region between the source and the drain under the influence of the potentials of the gate and the drain connected in series and integrated in a semiconductor chip to constitute a charge transfer train. The drain of one static induction transistor and the source of the next adjacent static induction transistor are integrated in common into a charge storage region. An insulated electrode is provided on each charge storage region to control the potential thereof. The charge transfer train can be driven by 4-phase, 3-phase or 2-phase signals. The gate electrodes and the drain electrode for each transistor may be integrated to form directional 2-phase charge transfer train. Image pick up device of very high operation speed can be materialized with the above charge transfer train.
    Type: Grant
    Filed: June 22, 1979
    Date of Patent: November 10, 1981
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4298869
    Abstract: A plurality of light-emitting diodes are connected in series to elevate the working voltage. A plurality of said series connection are connected in parallel to maintain display even upon a disconnection accident. The total number of light-emitting diodes provides a bright and failure-safe colored light display at a low power consumption. The conventional colored-light-emitting display can be easily substituted by the novel light-emitting diode display to reduce the power consumption and elongate the service lifetime.
    Type: Grant
    Filed: June 25, 1979
    Date of Patent: November 3, 1981
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Yasuo Okuno
  • Patent number: 4284997
    Abstract: In a static induction transistor, the gate structure is split into two separate gates facing each other to cooperatively define therebetween a channel or channels of this transistor. One of these two separate gates is operative as a driving gate for driving the transistor in response to a driving signal applied thereto, while the other one is operative as a non-driving gate which has no driving signal applied. The non-driving gate may be held at a certain potential or floated. Such split-gate structure provides a higher operating speed of the transistor, and can be effectively applied to semiconductor memory devices.In such a memory device having split-gate structures, a plurality of field effect type semiconductor memory cells are formed perpendicular to a surface of a semiconductor wafer to enhance a high packing density of the memory device.
    Type: Grant
    Filed: June 29, 1978
    Date of Patent: August 18, 1981
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4270059
    Abstract: A static induction transistor logic circuit comprising: an injector transistor having a control electrode held at a reference potential, a first electrode, and a second electrode applied with a potential to thereby cause a current having a value determined by the potential applied to flow through the first electrode; a driver static induction transistor having a gate connected to said first electrode of the injector transistor, a drain, and a source held at said reference potential; and a bypath static induction transistor having a gate, a drain connected to both the gate of the bypath transistor and said gate of said driver transistor, and a source held at said reference potential, said bypath transistor being operative so that when said driver transistor is in its conductive state, the bypath transistor becomes conductive to allow a part of said current supplied from said first electrode to flow through the bypath transistor, with a certain potential developed at the drain of the bypath transistor, said cer
    Type: Grant
    Filed: May 18, 1978
    Date of Patent: May 26, 1981
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventors: Jun-ichi Nishizawa, Tadahiro Ohmi
  • Patent number: 4266238
    Abstract: An improved transistor comprising an embedded electrode formed in a semiconductor substrate and having a high resistivity semiconductor region intervening between the embedded electrode and the substrate. The dimension and the impurity concentration of the high resistivity region are selected to insure that this latter region is substantially pinched off in the operative state of this transistor by the depletion layer growing from either the embedded electrode or the substrate, the width of said depletion layer varying in good faith without delay with the quick changes in the voltage of the embedded electrode. This provides an effective reduction mainly in the capacitance between the embedded electrode and the substrate, and also in the conductance in high-speed operation, which jointly bring about a high speed operation and a large driving ability. This transistor is extremely useful when adopted in a semiconductor integrated circuit.
    Type: Grant
    Filed: March 7, 1978
    Date of Patent: May 5, 1981
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4259681
    Abstract: An integrated circuit comprising an inversely operated static induction transistor capable of performing very high speed operation at low power dissipation. In an integrated injection logic circuit, at least one of the injection and the output transistor is formed of a static induction transistor which has small storage effect of minority carriers in the channel region.
    Type: Grant
    Filed: July 3, 1978
    Date of Patent: March 31, 1981
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4233109
    Abstract: A radio frequency and a static electric field are superposedly applied to a low pressure gas to generate a gaseous plasma and to drive ions of selected polarity in a predetermined direction. The processing chamber is pre-evacuated to a sufficiently high vacuum, and an etching gas is introduced into the chamber to be rendered to a low pressure at which the mean free path of the ions is sufficiently long. The pressure of the etching gas may range from the order of 10.sup.-2 Torr to several Torr for etching silicon, using a silicon oxide as a mask material.This method improves the treating accuracy, especially minimizes the amount of side etch, as compared with the conventional plasma etching, and reduces the surface damage when compared with the known ion beam etching.
    Type: Grant
    Filed: July 12, 1978
    Date of Patent: November 11, 1980
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Junichi Nishizawa
  • Patent number: 4198648
    Abstract: An integrated semiconductor device comprising: a first and a second static induction transistor each including a drain and a source, each having a first conductivity type, a current channel having the first conductivity type and located between the drain and the source, and a gate having a second conductivity type opposite to the first conductivity type and located adjacent to the current channel; and a third bipolar transistor including a collector and an emitter each having the second conductivity type, and a base having the first conductivity type and located between the collector and the emitter, the collector being connected to the gates of the first and second transistors and also to the drain of the second transistor, the source of the second transistor being connected to the source of the first transistor. The second transistor is operative for suppressing the occurrence of an unrequired excessive minority carrier injection in the first transistor.
    Type: Grant
    Filed: May 4, 1978
    Date of Patent: April 15, 1980
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4160259
    Abstract: In a transistor structure having a pair of current electrodes and a control electrode, at least one control electrode is added to vary the negative feed-back resistance in the current path. In a typical example, both the triode-like and the pentode-like characteristics are provided by the control in the voltage applied to the additional control electrode for varying the negative feed-back resistance r.sub.s, thereby changing the product G.sub.m .multidot.r.sub.s from less than unity to greater than unity where G.sub.m is the transconductance.
    Type: Grant
    Filed: December 27, 1976
    Date of Patent: July 3, 1979
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa
  • Patent number: 4115793
    Abstract: A field effect transistor having an additional highly doped source region contiguous to the source region and protruding into the channel having a shape approximately conforming to the shape of the depletion layer and almost contiguous with the depletion layer in a desired operative state, thereby reducing the series resistance from the source to the pinch-off point without increasing the capacitance between the source and the gate. The improvement is particularly effective for devices of a high power, high speed and high frequency use and is compatible with the integrated circuit techniques.
    Type: Grant
    Filed: November 29, 1977
    Date of Patent: September 19, 1978
    Assignee: Zaidan Hojin Handotai Kenkyu Shinkokai
    Inventor: Jun-ichi Nishizawa