Abstract: A receiver receives an ATV (e.g. HDTV) signal in an area that is subject to NTSC co-channel and other interference. The received signal is precoded at the transmitter for enabling reduction of NTSC co-channel interference in the received signal. The received signal includes field sync signals that are successively field combed to produce a subtraction signal. The subtraction signal is comb filtered to reduce NTSC co-channel interference and applied to a comparator along with the unfiltered subtraction signal. The comparator determines whether the level of NTSC co-channel interference is sufficiently great to subject the received ATV signal to comb filtering for reducing the NTSC co-channel interference.

Abstract: A television remote control system includes an on-screen cursor that is controllable by a viewer-operated remote transmitter. The remote transmitter includes a trackball that yields X,Y coordinate information responsive to rotational movement thereof and a switch that generates an activate signal responsive to depression of the trackball. A microprocessor in the television receiver controls the on-screen cursor display and updates the cursor position in response to transmitted IR X,Y position signals. A microprocessor in the remote transmitter monitors the trackball, the trackball operated switch and any other functional key switches. The television screen is divided into different control function areas and the areas are illuminated as each area is accessed by the cursor, i.e. as the designated cursor position impinges on the area. The cursor movement defined by the position signal is divided into a series of smaller movements to produce smooth cursor movements on the screen.

Abstract: A digital conditional access module for a subscriber terminal comprises a decryption device including at least one PID register and an associated countdown register. The decryption device is enabled for decrypting received product packets having a PID matching a PID stored in the PID register so long as the associated countdown register is characterized by a non-zero value. Decryption of a product packet results in the countdown register being decremented by a selected factor, the countdown register being prevented from assuming a zero value by setting its contents to a selected value in response to a received conditional access packet containing a PID matching the PID stored in the PID register. The selected value to which the countdown register is set may also be contained within the received conditional access packet.

Abstract: A trellis coded modulation system comprises a source of successive 2-bit data symbols X.sub.1, X.sub.2 arranged in a frame format wherein each frame comprises a plurality of data segments each including a plurality of groups of interleaved data symbols. Each group of interleaved data symbols is separately coded by a precoder and convolution encoder to derive coded output symbols Z.sub.0, Z.sub.1, Z.sub.2, which are mapped to respective 8-level symbols for transmission together with periodically generated frame and segment sync symbols. The received signal may be filtered by a linear filter, e.g. a comb filter, to reduce co-channel interference and each group of filtered symbols is applied to a respective first Viterbi decoder for estimating data bits X.sub.1 X.sub.2. Each first decoder preferably comprises a reduced complexity Viterbi decoder responsive to a partial representation of the state of the linear filter.

Abstract: A combination media ingress/egress door and display panel for a consumer electronics product is disclosed as having tunnels therein with openings for receiving light from controllable light sources mounted within the casing. The opposite end of the tunnels connect with the front face of the display panel. The front openings are fitted with lenses or overlays in the shape of the necessary information segments. Thus, the combination door and display panel has no electrical components or connections thereon which would be subject to undue mechanical stress which might cause failure of the display.

Abstract: An antenna adjustment system for a digital television receiver includes a graphics generator for receiving an error signal input and developing an on-screen signal quality display. An antenna is positionable by the viewer while referring to the on-screen signal quality display which enables optimal orientation of the antenna for best signal quality. The error signal is developed by comparing a rugged frame sync in the received television signal with a reference frame sync in the television receiver.

Abstract: A technique for enhancing the robustness of an ATV transmission system in the presence of NTSC or ATV co-channel interference comprises positioning the ATV signal relative to the co-channel NTSC/ATV signal to reduce interference into the ATV receiver. In a preferred embodiment, the ATV signal is positioned relative to a co-channel NTSC signal such that the demodulated difference f.sub.v -f.sub.p in the ATV receiver is equal to 70.5 f.sub.seg, where f.sub.v is the NTSC visual carrier frequency, f.sub.p is the ATV pilot carrier frequency and f.sub.seg is the ATV segment repetition rate, and relative to a co-channel ATV signal such that their respective pilot frequencies differ by an amount equal to 1.5 f.sub.seg.

Abstract: An arrangement of a video tape recording apparatus has a simplified motor and mechanical power transmission arrangement which yields benefits for cost, reliability and space savings by reducing the number of motors and moving parts necessary to provide an operable video tape recording or playback apparatus.

Abstract: An adaptive equalizer decision circuit for a digital television signal, including a field synchronizing signal, consisting of multilevel symbols and a DC offset representing a pilot. The variation of the DC level of the received signal during the field sync with respect to a predetermined threshold is derived for placing the equalizer in a training signal or data directed operating mode. Another approach determines the difference between a current value of the field sync and each of a plurality of values of the field sync in previous fields and determining therefrom whether the equalizer should be in its data directed mode of operation or in its training signal mode of operation. A modification consists in controlling the step size of the equalizer based upon either the DC level variation or the field sync differences of the received signal. The modification may be used alone or in combination with the equalizer operating mode control.

Abstract: Each of a plurality of terminals in a two-way communications system includes a series of counters establishing a plurality of time slots synchronized to a downstream reference parameter. Upstream transmissions are effected by each terminal in one or more of the time slots which are defined by a downloaded message as comprising either a reserved slot or a contention slot. The downloaded message, which may also establish terminal transmission power levels and retransmission backoff algorithms for contention time slots, is derived on the basis of the population of subscriber terminals and the usage of the upstream channel.

Abstract: A digital data processing system receives compressed variable length encoded digital data in the form of variable length codewords in contiguous variable speed Blocks of data. The boundary signals between adjacent codewords are determined and a demultiplexer sequentially sorts the serial digital data among a plurality of parallelly connected buffers for reducing the bit read speed of the buffers. A corresponding plurality of variable length decoders decodes the data from the buffers and outputs the data in parallel form to a multiplexer where it is reassembled into a serial expanded data stream. The incoming data includes selector information in fixed length headers that are separated, buffered and variable length decoded for controlling the demultiplexer. In one aspect of the invention, the data is sorted into substantially equal sized groups of integral codewords for equalizing the loading of the parallel buffers.

Abstract: An ATM/MPEG system receives individual MPEG programs of different constant bit rates from a plurality of servers. The individual programs are converted into ATM cells which are transmitted along an ATM network at a constant bit rate. The ATM cells are received and arranged into queues of the individual programs. A microprocessor prioritizes the queues based upon the bit rates of the MPEG programs. The queues are multiplexed to 16 VSB modulators based upon their priority assignments with the highest priority queues being sent to the modulators in preference to lower priority queues.

Abstract: A tri-state controlled video switch includes three switch transistors, each being coupled to a common output line and each being supplied with a different video input signal. A microprocessor controls the voltage condition on a control line. In response to a high, low or open voltage condition on the control line, an arrangement of transistors controls the operation of the switch transistors such that only a corresponding one of the three video signals is coupled to the common output line.

Abstract: An apparatus and method for forming color video display screens of the line or stripe screen type are disclosed. Tubules form menisci of screen element liquids which are contacted with a moving display screen surface to produce screen element lines comprising the screen.

Abstract: A gain control circuit utilizes a PWM having its transfer function characteristics determined by a ramp and a DC supply voltage. An input signal modulates the PWM and an integrating circuit at the output of the PWM recovers a replica of the input signal. Changing one or more of the transfer function characteristics of the PWM results in a change in the amplitude of the recovered replica of the input signal. Changing the ramp frequency may also be used to effect gain control. An arrangement in a television deflection circuit with raster correction is shown.

Abstract: A cable ready television receiver includes a set back decoder that communicates with the microprocessor in the television receiver via its own microprocessor. A synchronous demodulator in the television receiver is operated normally for unscrambled television signals and is operated to quadrature demodulate scrambled television signals. The quadrature demodulation develops only high frequency video, modulated chroma, FM modulated audio and DC. The demodulator output is applied to the audio circuit and to the AGC circuit in the television receiver. A descrambler in the decoder develops the video signal for application to the video circuitry in the television receiver.

Abstract: A dual mode AGC system for a television receiver in which data is in the form of symbols occurring at a fixed symbol rate. The symbols are sent in successive data segments, each having a sync character. Enablement of an AFC Defeat signal defines an initial interval during which the IF gain is maximum. When the AFC Defeat signal becomes inactive, the receiver is operated in a non-coherent mode in which the gain of the IF amplifier is reduced incrementally whenever the IF signal exceeds a clipping level for a period of eight successive symbol clocks. Upon a segment sync lock condition occurring, a normal coherent mode is entered in which the AGC responds to a signal characteristic, i.e. data segment sync. The rate of gain change available in the non-coherent mode-is much greater than that in the normal coherent mode.

Abstract: A television receiver is equipped with hardware/firmware so that it may be disabled by a remotely transmitted series of codes. In a preferred embodiment, the display of the receiver indicates that the receiver is operable, but has been disrupted, rather than being broken. The invention is particularly useful for commercial situations such as rentals or lodging facilities where payment is expected for use of the television.

Abstract: A cable television upstream data transmission system provides a plurality of time slots synchronized to the downstream symbol clock for use by subscriber terminals in upstream data transmission. The width and number of time slots are controlled by a pair of downloadable values to accommodate dynamic changes of the cable system. A transmission modulator used within the subscriber terminal produces an upstream transmission carrier having a frequency locked to the symbol clock. The frequency of the carrier signal produced by the transmission modulator is programmably controlled by a plurality of program values which are selected to provide frequency and phase lock of the modulator's carrier to the symbol clock.

Abstract: A network interface card for a personal computer includes a controller chip and a programmable logic array that is coupled at its output terminals to the bus pull-up resistors, or to dedicated terminals of the controller chip for establishing different configurations for the controller chip on the interface card. A rotary, ten position binary coded decimal switch is coupled across the inputs of the programmable logic array. Each position of the switch establishes a different configuration for the controller. The arrangement eliminates the need for manual switches and movable jumpers for configuring the network interface card controller chip.