Abstract: A method and system for enhancing a digital input signal and producing a modified digital output signal that can either be further digitally processed or that can be converted to an analog signal. A digital input signal passes through a low-pass filter, a high-pass filter and a bandpass filter. A digital signal emitted from a high-pass section of the bandpass filter is delivered to a dynamically-controlled multiplier operating in a digital domain. Digital signals emitted from the low-pass filter, the high-pass filter and the bandpass filter are summed with a signal multiplied by the dynamically-controlled multiplier. A process controller and a contour controller can be used to vary low-frequency boost and high-frequency boost delivered by the modified digital input signal which can then be converted to an analog audio output sample.

Abstract: A digital video communication system includes a two-way communication link between a source and a viewer. A video program, in sequential compressed digital form, is repetitively supplied to a fifo memory that has taps corresponding to the number of fixed length segments in the video program. The program is taken from one of the taps and supplied to a one segment-long fifo memory which has taps corresponding to fields in the segment. A program request by a viewer results in the segment at which the beginning of the program will next appear to be addressed and remembered. The field fifo is reset to the first tap and the video program data is processed and transmitted to the viewer from the first field tap. Should the viewer wish to interrupt the video program, a field counter is enabled by an interrupt signal to step over the field taps (at the field rate), thus "freezing" the program. The interrupt signal also causes the address counter to count up (change tap addresses) at the segment rate.

Abstract: A high voltage focus potentiometer module includes a housing having a plurality of connection cavities and corresponding wire guides formed therein. A substrate is secured within the housing. The substrate includes the stationary elements of the potentiometer, the wiper of which is located in a recess that is surrounded by a flexible seal. Conductive rubber inserts are loosely fitted in the cavities and are adapted to be piercingly engaged by wires in the wire guides and in contact with corresponding conductive pads on the substrate. Channels are provided in the housing to permit flowable epoxy to surround the conductive rubber inserts and wires in the cavities. A high voltage transformer includes a shell having an open side to which the potentiometer module is snap-fitted. A conductive element on the transformer is positioned in the open side and is adapted to be piercingly engaged by a conductive rubber plug that also engages a conductive pad on the other side of the substrate.

Abstract: An input signal of frequency tolerance A is combined with a reference first signal having a frequency tolerance B to develop a second signal having a combined frequency tolerance of -A and B . The input signal is combined with the second signal to offset and cancel the A and -A frequency tolerances to produce an output signal having a B frequency tolerance.

Abstract: A remote control device for a television receiver or the like includes a housing that defines a cavity. IR emitter-detector pairs are arranged about the cavity to establish an x-y pattern of IR beams within the cavity. Interruption of the IR beams by an opaque object, such as a human finger, activates signal generating means for generating control signals.

Abstract: A web television includes a monitor, a communication bus, an internet module, a tuner, and a television controller. The internet module is coupled to the communication bus, and is arranged to provide internet video for display on the monitor. The internet video is derived from internet communications between the internet module and internet content providers. The tuner is arranged to select television video for display by the monitor. The television controller is coupled to the communication bus, the television controller is arranged to switch the monitor between the internet video and the television video, the television controller receives character data from a remote control device, and the television controller transmits the received character data over the communication bus to the internet module in a message containing a last received character datum and a current received character datum.

Abstract: A vertical sync separator circuit that operates with signals that have different arrangements of horizontal equalizing pulses in the vertical interval. The composite signal is integrated and used to operate a Schmidt trigger/inverter that feeds the data input of a D flip/flop. The flip/flop is clocked by the horizontal equalizing pulse that occurs after the beginning of the vertical pulse. In an arrangement that operates without equalizing pulses, a second trigger circuit is operates from a less than one-half line delay and supplies the reset input of the flip/flop. The arrangement provides consistent development of the vertical sync output pulse.

Abstract: A technique and apparatus for developing AGC voltage in a receiver capable of receiving VSB signals that do not have the data symbol levels and the sync symbol levels related so as to produce the same average magnitude level. Successive portions of the signal are accumulated, stored and compared with the smaller of the samples to be used to develop the AGC voltage. By comparing the first and third of three successive samples, the effect of the larger than desired sync levels in the over-the-air VSB signals is completely eliminated.

Abstract: An attenuator for signals in the frequency band of 50 to 800 MHz is subject to a range of AGC signal attenuating potentials. The attenuator includes a first attenuating PIN diode connected in series between an input and an output. The opposite ends of the first PIN diode are AC coupled via second and third impedance matching PIN diodes to an AC ground. The first PIN diode exhibits a frequency dependent slope over the wide signal frequency band and the range of AGC potentials. First and second inductors, in the form of metallic foil strips, are connected between the second and third PIN diodes and the AC ground. The foil strips are positioned in close proximity to each other and arranged such that signal currents flow therein in opposite directions to establish a negative mutual coupling coefficient for compensating for the frequency dependent slope of the first PIN diode.

Abstract: The self-cleaning wire stripper includes a wire stripping element, such as an RF coil, which burns insulation from a segment of wire. A wire guide, such as a insulating burn tube, positioned within the wire stripping element guides the wire through the wire stripping element. The self-cleaning wire stripper uses a reamer having a wire channel such that the wire passes through the reamer. At the desired time, such as at the end of every burn operation, the reamer cleans the wire guide, resulting in no down time for tube removal/cleaning. The reamer cycle time is transparent to the process and does not slow down throughput because reaming occurs during the coil winding process.

Abstract: A VSB mode detection circuit with a comb filter solves the potential problem of lockout in a situation where an 8 VSB mode signal is being received, with the comb filter being effective, and a change in signal mode suddenly occurs. The arrangement inhibits the first two bytes of the three byte mode information, which two bytes are unspecified for all except the 8 VSB terrestrial mode, and replaces them with zero data. In another embodiment, the 12 symbol delay in the comb filter is bypassed with the complement of the input data for the third byte. When the 8 VSB terrestrial mode has been confidently determined to exist, the inhibition of the first and second bytes (and the inversion of the bypassed third byte) is removed in alternate fields to permit normal comb filter operation.

Abstract: The frequency roll-off experienced by video signals applied to the three cathodes of a color cathode ray tube, due to the capacitance between the cathodes and the common control grid, is compensated with a single inductor connected in series with the common control grid.

Abstract: An interface for coupling 19.39 MHz serial packetized transport data in MPEG form to parallel transport data having a maximum symbol rate of 10.76 megasymbols per second. The incoming data includes filler packets to assure that the input bit rate is always in excess of a nominal bit rate. A serial/parallel decoder generates packetized parallel data which is applied to a packet remover. A buffer of multi packet capacity is periodically read to determine its fullness. Packets are removed as required to maintain the desired input bit rate. The buffer supplies a filler packet inserter that is also operated in accordance with the buffer fullness to assure an optimized output packetized data stream of symbols that does not exceed a maximum symbol rate.

Abstract: A digital television receiver operating in the presence of an NTSC co-channel signal includes an NTSC rejection filter that is selectively inserted in the digital television signal path to minimize interference from the NTSC co-channel signal. The energy around the NTSC picture carrier is sampled. This is compared with sampled white noise energy between the NTSC picture and color carriers, after field combing the digital television signal to eliminate the effects of static signals. The comparison is used to determine whether or not the NTSC rejection filter is inserted in the digital television signal path.

Abstract: A first station encodes data as data symbols, rotates the data symbols so that data symbols corresponding to one another across sync portions of data segments of a frame are arranged to be processed together, and inserts the rotated data symbols into data portions of the data segments of the frame such that the frame has a plurality of data segments, wherein each data segment has a segment sync portion and a data portion. A second station processes the data symbols so that corresponding data symbols in a first set of data symbols are processed with a twelve data symbol delay and corresponding data symbols in a second set of data symbols are processed with a twenty-four data symbol delay depending upon the position of the data symbols in relation to the sync portions.

Abstract: A receiver for decoding encoded data transmitted by a transmitting station includes (i) sum and difference filters for filtering the encoded data and for providing corresponding sum and difference filtered outputs, (ii) first and second variable gain amplifiers for respectively controlling the sum and difference filtered outputs so as to provide corresponding sum and difference controlled filtered outputs that vary along a continuum in order to suppress co-channel interference and white Gaussian noise in the encoded data, and (iii) a Viterbi decoder for decoding the sum and difference controlled filtered outputs to recover uncoded data.

Abstract: The improved convergence core assembly utilizes a separate carriage for the convergence core. This separate carriage properly aligns and holds the convergence core in relation to the convergence core assembly. In particular embodiments, the separate core carriage provides self centering and positional stability for the convergence core in the x-y plane, in the z-axis, and rotationally in the x-y plane. To accomplish this, the core carriage includes means for positioning the convergence core in the convergence core assembly. In certain embodiments, the means for positioning includes leaf springs and positioning tabs. The leaf springs tend to force the electromagnetic coil assembly against the stops of the positioning tabs to properly locate the convergence core in the z-axis. The positioning tabs also exert opposing spring forces on the convergence core to center the convergence core assembly in the x-y plane.

Abstract: A biphase stable FPLL includes a lock switch, operated in response to a frequency lock condition, that forces a predetermined voltage on the input of the third multiplier to guarantee that the loop locks up in a phase that produces a desired polarity of demodulated signal. A frequency lock indicator operates the lock switch to force the predetermined voltage on the third multiplier irrespective of the actual lock up phase of the loop. If the lock up phase is wrong, the voltage reversal causes the VCO to slip 180.degree. in phase and the loop locks up in its other bistable state.

Abstract: A DC removal circuit for removing residual DC from a digitally encoded television signal including a plurality of multi level data symbols occurring at a constant symbol rate and formatted in repetitive data fields, each field including repetitive data segments having data segment sync of a fixed pattern of four symbols. A derived value of DC is subtracted from each of the received data symbols. The output of the subtractor is sampled, at the symbol rate or at one-half the symbol rate, and the sampled output is accumulated in an accumulator for generating the derived value. The sampling is continuous. The accumulator is preset to a zero value upon tuning to a different channel. An equalizer is supplied with the derived value of DC.