Abstract: An example apparatus includes at least one programmable circuit to analyze workload runs for a plurality of combinations of enabled setting to determine a subset of the plurality of combinations that satisfy a target performance metric; run a workload for a second combination of enabled settings to generate a result, the second combination combining enabled settings from two or more of the subset of the plurality of combinations; analyze the result to determine the second combination satisfies the target performance metric; and deploy the second combination and the subset of the plurality of combinations to a device to process a second workload using at least one of the second combination of the subset of the plurality of combinations.

Abstract: This disclosure describes systems, methods, and devices related to multi-link device (MLD) data continuity. An MLD device may set up one or more links with a station multi-link device (STA MLD), wherein the STA MLD comprises one or more logical entities defining separate station devices. The MLD device may transmit a data packet associated with a traffic identifier (TID) to the STA MLD. The MLD device may determine that the data packet was not received by the STA MLD. The MLD device may retransmit the data packet to the STA MLD. The MLD device may increment a retransmit counter every time the data packet is retransmitted. The MLD device may refrain from transmitting a second data packet until the data packet is dropped or successfully received by the STA MLD.

Abstract: A computing platform comprising a plurality of disaggregated data center resources and an infrastructure processing unit (IPU), communicatively coupled to the plurality of resources, to compose a platform of the plurality of disaggregated data center resources for allocation of microservices cluster.

Abstract: Described herein are technique to enable the autonomous generation of configurations for a network environment, including but not limited to an edge network of a datacenter. Additional embodiments include prompt-based generation of network and device configurations and neural network based systems for adaptive network management.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.

Abstract: Described herein is a graphics processor comprising a graphics processing cluster coupled with the memory interface, the graphics processing cluster including a plurality of processing resources, a processing resource of the plurality of processing resources including a register file including a first plurality of registers associated with a first hardware thread of a plurality of hardware threads of the processing resource and a second plurality of registers associated with a second hardware thread of the plurality of hardware threads of the processing resource and first circuitry configured to facilitate access to memory on behalf of the plurality of hardware threads and store metadata for memory access requests from the plurality of hardware threads.

Abstract: Methods and apparatus relating to techniques for region-based deterministic memory safety are described. In some embodiment, one or more instructions may be used to encrypt, decrypt, and/or check a pointer to a portion of the data stored in memory. The portion of the data is stored in a first region of the memory. The first region of the memory includes a plurality of identically sized allocation slots. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to tall Dual Inline Memory Module (DIMM) structural retention are described. In one embodiment, a Dual In-Line Memory Module (DIMM) retention frame is coupled to a top portion of a tall (e.g., “two unit” or taller) DIMM. A plurality of fasteners physically attach the DIMM retention frame to a Printed Circuit Board (PCB). The DIMM retention frame reduces movement of the tall DIMM. Other embodiments are also claimed and disclosed.

Abstract: Examples described herein relate to a cold plate. An example apparatus includes a first layer with one or more channels to receive fluid. The example apparatus further includes a second layer that is more rigid than the first layer. The second layer is to be mounted to the first layer and separated from the first layer by a gasket to reduce corrosion of the second layer.

Abstract: A system includes memory circuitry to store a secure shared memory buffer (SSMB) and instructions; and a processor to create the SSMB in the memory circuitry and assign ownership of the SSMB to an SSMB owner, the SSMB owner being a trusted execution environment virtual machine running on the computing system; configure access permissions for the SSMB by the SSMB owner to allow one or more SSMB users to access the SSMB, the one or more SSMB users being trusted execution environment virtual machines running on the computing system; allocate memory by the SSMB owner from the SSMB owner's private memory space in the memory circuitry for the SSMB; and allowing secure access by the one or more SSMB users to the SSMB in response to successfully verifying authorization of the one or more SSMB users based at least in part on the access permissions.

Abstract: For example, a wireless communication device may be configured to generate a wide bandwidth Long Training Field (LTF) configured for channel sounding over a wide channel bandwidth of at least 320 Megahertz (MHz). For example, the wide bandwidth LTF may include a plurality of Orthogonal Frequency Division Multiplexing (OFDM) symbols over the wide channel bandwidth. For example, the wireless communication device may be configured to transmit a Null Data Packet (NDP) over the wide channel bandwidth. For example, the NDP may include a non-High-Throughput (non-HT) Short Training Field (L-STF), a non-HIT LTF (L-LTF) after the L-STF, a non-HT Signal (L-SIG) field after the L-LTF, a Repeated L-SIG (RL-SIG) field after the L-SIG field, and the wide bandwidth LTF after the RL-SIG field.

Abstract: Management of data transfer for network operation is described. An example of an apparatus includes one or more network interfaces and a circuitry for management of data transfer for a network, wherein the circuitry for management of data transfer includes at least circuitry to analyze a plurality of data elements transferred on the network to identify data elements that are delayed or missing in transmission on the network, circuitry to determine one or more responses to delayed or missing data on the network, and circuitry to implement one or more data modifications for delayed or missing data on the network, including circuitry to provide replacement data for the delayed or missing data on the network.

Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, a method for forming an IC package support may include forming a first dielectric material having a surface; forming a first conductive via in the first dielectric material, wherein the first conductive via has tapered sidewalls with an angle that is equal to or less than 80 degrees relative to the surface of the first dielectric material; forming a second dielectric material, having a surface, on the first dielectric material; and forming a second conductive via in the second dielectric material, wherein the second conductive via is electrically coupled to the first conductive via, has tapered sidewalls with an angle that is greater than 80 degrees relative to the surface of the second dielectric material, and a maximum diameter between 2 microns and 20 microns.

Abstract: Described herein is a graphics processor comprising first circuitry configured to execute a decoded instruction and second circuitry configured to second circuitry configured to decode an instruction into the decoded instruction. The second circuitry is configured to determine a number of registers within a register file that are available to a thread of the processing resource and decode the instruction based on that number of registers.

Abstract: Disclosed herein are radio frequency (RF) front-end structures, as well as related methods and devices. In some embodiments, an RF front-end package may include an RF package substrate including an embedded passive circuit element. At least a portion of the embedded passive circuit element may be included in a metal layer of the RF package substrate. The RF package substrate may also include a ground plane in the metal layer.

Abstract: An apparatus includes a host interface; a network interface; and a programmable circuitry communicably coupled to the host interface and the network interface, the programmable circuitry comprising one or more processors to implement network interface functionality and to: determine portions of a set of computer vision (CV) processes to be deployed on the programmable circuitry and a host device, wherein the host device to be communicably coupled to the programmable network interface device; access instructions to cause the portions of the set of the CV processes to be deployed on the host device and the programmable network interface device; and wherein a media processing portion of the set of the CV processes is to be deployed to the programmable circuitry, and wherein the programmable circuitry is to utilize media processing hardware circuitry hosted by the apparatus to perform the media processing portion.

Abstract: Techniques to form semiconductor device conductive interconnections. In an example, an integrated circuit includes a recessed via and a conductive bridge between a top surface of the recessed via and an adjacent source or drain contact. A transistor device includes a semiconductor material extending from a source or drain region, a gate structure over the semiconductor material, and a contact on the source or drain region. Adjacent to the source or drain region, a deep via structure extends in a vertical direction through an entire thickness of the gate structure. The via structure includes a conductive via that is recessed below a top surface of the conductive contact. A conductive bridge extends between the contact and the conductive via such that the conductive bridge contacts a portion of the contact and at least a portion of a top surface of the conductive via.

Abstract: In one embodiment, a display panel may have multiple regions that are controlled by independent driver circuitries to allow for independent refreshing of different regions. Circuitry, e.g., in a graphics source or in the display, can determine, based on a partial frame update, which panel regions to refresh and refresh those regions, e.g., while not refreshing other regions of the panel.

Abstract: Methods and apparatus to reduce cracking in glass cores are disclosed. An example apparatus includes a package substrate comprising a glass core having an opening extending between first and second surfaces of the glass core, the first surface opposite the second surface, and a conductive material, a first portion of the conductive material within the opening, a second portion of the conductive material protruding beyond the first surface of the glass core, a first surface of the first portion in continuity with a second surface of the second portion.

Abstract: For example, a wireless communication station (STA) may be configured to determine a selected setting of one or more rate-dependent parameters for transmission of a Physical layer (PHY) Protocol Data Unit (PPDU) based on a minimal Medium Access Control (MAC) Protocol Data Unit (MPDU) size requirement such that, for at least one MPDU of the PPDU, a first count of MAC padding bits to pad the MPDU according to the selected setting of the one or more rate-dependent parameters is less than a second count of MAC padding bits to pad the MPDU according to a channel-based setting of the one or more rate-dependent parameters, wherein, the channel-based setting of the one or more rate-dependent parameters is based on a condition of a wireless communication channel for transmission of the PPDU; and to transmit the PPDU according to a transmission data rate based on the selected setting.

Abstract: For example, a current consumption adjuster may be configured to adjust a current consumption from a power supply of an integrated circuit. For example, the current consumption adjuster may include a controllable load circuitry to controllably apply one or more loads to the power supply of the integrated circuit. For example, the current consumption adjuster may include a controller configured to identify a current consumption event including a transition of a current consumption of the integrated circuit from the power supply. For example, the controller may be configured to control activation of the controllable load circuitry to apply an event-based load to the power supply, for example, based on the current consumption event.

Abstract: One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

Abstract: Key-value (KV) cache paging schemes can improve memory management for KV caches by storing a KV cache page having key tensors and value tensors for a fixed number of tokens in a fixed-sized block in the KV cache of a worker. To further improve memory management, the schemes can be modified to implement dynamic variable quantization. Quantization level of a KV cache page can be set based on a runtime importance score of the KV cache page. In addition, the quantization level of the KV cache page can be set based on the system load. The end result is a scheme that can achieve a high compression ratio of KV cache pages in the KV cache. Fitting more KV cache pages in the KV cache can lead to higher inference throughput, higher system-level user capacity, and higher end-to-end service availability.

Abstract: This disclosure describes systems, methods, and devices related to optimized resource technologies. A device may create a Managed Object Instance (MOI) representing actions executed based on artificial intelligence or machine learning (AI/ML) inference function. The device may notify a management and network service (MnS) consumer about the creation of the MOI. The device may execute actions by a network or management function acting as the consumer of the inference output. The device may manage performance of the AI/ML inference function.

Abstract: For example, a non Access Point (AP) (non-AP) Multi-Link Device (MLD) may be configured to assign a first priority to a first link of a multi-link operation mode and a second priority to a second link of the multi-link operation mode. For example, the first priority assigned to the first link of the multi-link operation mode may be higher than the second priority assigned to the second link of the multi-link operation mode. For example, the non-AP MLD may be configured to limit a transmission from the non-AP MLD over the second link based, for example, on a busy state of a wireless communication medium of the first link.

Abstract: Embodiments are generally directed to methods and apparatuses of spatially sparse convolution module for visual rendering and synthesis. An embodiment of a method for image processing, comprising: receiving an input image by a convolution layer of a neural network to generate a plurality of feature maps; performing spatially sparse convolution on the plurality of feature maps to generate spatially sparse feature maps; and upsampling the spatially sparse feature maps to generate an output image.

Abstract: Embodiments of a semiconductor die comprise: a first bond-pad on a first surface to couple to a package substrate, a second bond-pad on a second surface, the second surface being opposite to the first surface, a hole through the semiconductor die, a conductive pillar within the hole separated from sidewalls of the hole by an air gap, the conductive pillar coupled to the first bond-pad and the second bond-pad, and pathways conductively coupling at least two integrated circuit (IC) dies proximate to the second surface.

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Abstract: A method comprises establishing, in a trusted security manager of a trusted execution environment, a device update pre-authentication policy for a device communicatively coupled to the trusted execution manager, providing the device update pre-authentication policy to the device, receiving, from the device, a pre-authentication event signal, and providing, to the device, a pre-authentication event response comprising an update indicator to indicate to the device whether a runtime update may be performed.

Abstract: An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to sparsify a base model of a foundation model to generate a sparse base model, apply a neural low-rank adapter search to the sparse base model, and output a fine-tuned base model based on application of the neural low-rank adapter search to the sparse base model.

Abstract: This disclosure describes systems, methods, and devices related to pre-association exchange. A device may receive a physical layer (PHY) based extended long range (ELR) request from a station device (STA) within a transmission opportunity (TxOP). The device may allocate a unique Unassociated ID (UID) to the STA within the same TxOP, the UID being distinct among active unassociated devices. The device may indicate to the STA to use the UID in subsequent communications until association or a predefined timeout occurs. The device may cause to send a trigger frame to the STA using the UID for scheduled uplink transmissions.

Abstract: A data processing unit may include a memory, processing elements (PEs), and a control unit. The memory may store weight blocks within a weight tensor of a neural network operation. Each weight block has an input channel (IC) dimension and an output channel (OC) dimension and includes subblocks. A subblock includes one or more weights having a first data precision and one or more other weights having a second data precision. The second data precision is lower than the first data precision. The control unit may distribute different ones of the subblocks to different ones of the PEs. A PE may receive a subblock and perform a first MAC operation on a weight having a first data precision and a second MAC operation on a weight having a second data precision. The first MAC operation may consume more computation cycles or more multipliers than the second MAC operation.

Abstract: One embodiment provides for a machine-learning accelerator device a multiprocessor to execute parallel threads of an instruction stream, the multiprocessor including a compute unit, the compute unit including a set of functional units, each functional unit to execute at least one of the parallel threads of the instruction stream. The compute unit includes compute logic configured to execute a single instruction to scale an input tensor associated with a layer of a neural network according to a scale factor, the input tensor stored in a floating-point data type, the compute logic to scale the input tensor to enable a data distribution of data of the input tensor to be represented by a 16-bit floating point data type.

Abstract: Embodiments described herein provide a scalable coherency tracking implementation that utilizes shared virtual memory to manage data coherency. In one embodiment, coherency tracking granularity is reduced relative to existing coherency tracking solutions, with coherency tracking storage memory moved to memory as a page table metadata. For example and in one embodiment, storage for coherency state is moved from dedicated hardware blocks to system memory, effectively providing a directory structure that is limitless in size.

Abstract: Photonic devices, packages, and systems with sub-surface compound microlenses are disclosed. An example microlens structure includes a glass core and a microlens stack embedded in the glass core, the stack comprising a plurality of regions stacked a direction of propagation of light that is to be manipulated by the microlens structure, wherein each region is a region of a substantially uniform refractive index that is different from the refractive index of the glass core. Such a stack may be referred to as a “sub-surface compound microlens,” where the term “sub-surface” is indicative of the fact that the stack may be below all surfaces of the glass core (i.e., is embedded in the glass core) and the term “compound” is indicative of the fact that the stack is a compound arrangement of multiple regions (e.g., each region is an individual microlens).

Abstract: For example, a wireless communication station (STA) may be configured to determine a usage-based channel Bandwidth (BW) setting, for example, based on a link-usage parameter corresponding to a usage of a wireless communication link for communication of traffic between the STA and an Access Point (AP). For example, the STA may be configured to transmit a channel BW reduction request to the AP, for example, based on a determination that the usage-based channel BW setting is less than an operating channel BW setting for the STA. For example, the channel BW reduction request may be configured to request the AP to reduce the operating channel BW setting for the STA based on the usage-based channel BW setting.

Abstract: Gesture-controlled virtual reality systems and methods of controlling the same are disclosed herein. An example apparatus includes an on-body sensor to output first signals associated with at least one of movement of a body part of a user or a position of the body part relative to a virtual object and an off-body sensor to output second signals associated with at least one of the movement or the position relative to the virtual object. The apparatus also includes at least one processor to generate gesture data based on at least one of the first or second signals, generate position data based on at least one of the first or second signals, determine an intended action of the user relative to the virtual object based on the position data and the gesture data, and generate an output of the virtual object in response to the intended action.

Abstract: Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICS. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

Abstract: A mechanism is described for facilitating misuse index for explainable artificial intelligence in computing environments, according to one embodiment. A method of embodiments, as described herein, includes mapping training data with inference uses in a machine learning environment, where the training data is used for training a machine learning model. The method may further include detecting, based on one or more policy/parameter thresholds, one or more discrepancies between the training data and the inference uses, classifying the one or more discrepancies as one or more misuses, and creating a misuse index listing the one or more misuses.

Abstract: Methods, apparatus, systems and articles of manufacture for distributed use of a machine learning model are disclosed. An example edge device includes a model partitioner to partition a machine learning model received from an aggregator into private layers and public layers. A public model data store is implemented outside of a trusted execution environment of the edge device. The model partitioner is to store the public layers in the public model data store. A private model data store is implemented within the trusted execution environment. The model partitioner is to store the private layers in the private model data store.

Abstract: This disclosure describes systems, methods, and devices for probabilistic constellation shaping in wireless transmissions may include a device configured to generate, using a first quadrature amplitude modulation (QAM) order shaping encoder associated with a first code rate, shaped amplitude bits; generate, using a forward error correcting (FEC) encoder and a second code rate smaller than the first code rate, parity bits for the shaped amplitude bits; cause to transmit, using a channel, a first portion of the parity bits as sign bits for the shaped amplitude bits; and cause to transmit, using the channel, a second portion of the parity bits.

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to improve performance of a computing device implementing an exponential function. An example apparatus includes interface circuitry to obtain an input, computer readable instructions, and programmable circuitry to instantiate range reduction circuitry to determine, based on the input, a first range reduced argument and an accuracy control value for an approximation of the exponential function of the neural network, and determine, based on the first range reduced argument, a second range reduced argument for the approximation of the exponential function, the second range reduced argument having a smaller data range than the first range reduced argument, and exponential configuration circuitry to compute an exponential value of the input based on the accuracy control value and an exponential value of the second range reduced argument.

Abstract: Techniques are provided herein for identifying the user of audio earbuds. In particular, a wearer's head filters an audio signal, and the audio filtering capabilities of a user's head are used as a biometric feature. One earbud can be used as an audio emitter and the other earbud as an audio receiver. A broadband sound can be generated by the speaker in one earbud and received at the microphone of the other earbud. The received sound is filtered by the user's head and the head characterization of the received filtered sound can be used to identify the user. In particular, the material properties of the user's head change the signal, such that the received signal at the microphone of the other earbud is different from the transmitted signal. The differences are unique to the user's head due to physiological variances among people, and can be used to identify the user.

Abstract: Embodiments of apparatuses, methods, and systems for highly scalable accelerators are described. In an embodiment, an apparatus includes an interface to receive a plurality of work requests from a plurality of clients and a plurality of engines to perform the plurality of work requests. The work requests are to be dispatched to the plurality of engines from a plurality of work queues. The work queues are to store a work descriptor per work request. Each work descriptor is to include all information needed to perform a corresponding work request.

Abstract: One embodiment provides an apparatus comprising an interconnect fabric comprising a processing cluster including an array of multiprocessors coupled to an interconnect fabric, scheduling circuitry to distribute a plurality of thread groups across the array of multiprocessors, each thread group comprising a plurality of threads. A first multiprocessor of the array of multiprocessors can be assigned to process a first thread group comprising a first plurality of threads including a first thread sub-group and a second thread sub-group. The second thread sub-group has a data dependency on the first thread sub-group and the first multiprocessor includes circuitry to cause threads of the second thread sub-group to sleep until the threads of the first thread sub-group have satisfied the data dependency.

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

Abstract: A mechanism is described for facilitating slimming of neural networks in machine learning environments. A method of embodiments, as described herein, includes learning a first neural network associated with machine learning processes to be performed by a processor of a computing device, where learning includes analyzing a plurality of channels associated with one or more layers of the first neural network. The method may further include computing a plurality of scaling factors to be associated with the plurality of channels such that each channel is assigned a scaling factor, wherein each scaling factor to indicate relevance of a corresponding channel within the first neural network. The method may further include pruning the first neural network into a second neural network by removing one or more channels of the plurality of channels having low relevance as indicated by one or more scaling factors of the plurality of scaling factors assigned to the one or more channels.

Abstract: A processor implementing techniques for processor extensions to protect stacks during ring transitions is provided. In one embodiment, the processor includes a plurality of registers and a processor core, operatively coupled to the plurality of registers. The plurality of registers is used to store data used in privilege level transitions. Each register of the plurality of registers is associated with a privilege level. An indicator to change a first privilege level of a currently active application to a second privilege level is received. In view of the second privilege level, a shadow stack pointer (SSP) stored in a register of the plurality of registers is selected. The register is associated with the second privilege level. By using the SSP, a shadow stack for use by the processor at the second privilege level is identified.