Intel Patents
Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.
Intel Patents by Type- Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
- Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
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Patent number: 7193253Abstract: Embodiments of a transition metal alloy having an n-type or p-type work function that does not significantly shift at elevated temperature. The disclosed transition metal alloys may be used as, or form a part of, the gate electrode in a transistor. Methods of forming a gate electrode using these transition metal alloys are also disclosed.Type: GrantFiled: August 11, 2005Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Mark Doczy, Nathan Baxter, Robert S. Chau, Kari Harkonen, Teemu Lang
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Patent number: 7194634Abstract: In an embodiment of the present invention, a technique is provided for remote attestation. An interface maps a device via a bus to an address space of a chipset in a secure environment for an isolated execution mode. The secure environment is associated with an isolated memory area accessible by at least one processor. The at least one processor operates in one of a normal execution mode and the isolated execution mode. A communication storage corresponding to the address space allows the device to exchange security information with the at least one processor in the isolated execution mode in a remote attestation.Type: GrantFiled: February 26, 2001Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Carl M. Ellison, Roger A. Golliver, Howard C. Herbert, Derrick C. Lin, Francis X. McKeen, Gilbert Neiger, Ken Reneris, James A. Sutton, Shreekant S. Thakkar, Millind Mittal
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Patent number: 7193965Abstract: Techniques for supporting multiple potentially overlapping wireless protocols with a single electronic system are disclosed. In the description that follows, the overlapping protocols are Bluetooth and IEEE 802.11 for wireless networking; however, other overlapping protocols can be supported in a similar manner. A transaction control policy and a collision map are provided to determine which protocol to enable/disable when a conflict arises. Based on the transaction control policy and the collision map, one or more transceivers that operate according to the wireless protocols can be selectively enabled/disabled to avoid actual conflicts.Type: GrantFiled: May 4, 2000Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Ron Nevo, Xudong Zhao, Dror Shindelman, Michael Vakulenko, Ephraim Zehavi
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Patent number: 7194581Abstract: A memory agent may include a first port and a second port, wherein the memory agent is capable of detecting the presence of another memory agent on the second port. A method may include performing a presence detect operation on a first port of a memory agent, and reporting the results of the presence detect operation through a second port of the memory agent.Type: GrantFiled: June 3, 2003Date of Patent: March 20, 2007Assignee: Intel CorporationInventor: Pete D. Vogt
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Patent number: 7192856Abstract: Complementary metal oxide semiconductor metal gate transistors may be formed by depositing a metal layer in trenches formerly inhabited by patterned gate structures. The patterned gate structures may have been formed of polysilicon in one embodiment. The trenches may be filled with metal by surface activating using a catalytic metal, followed by electroless deposition of a seed layer followed by superconformal filling bottom up.Type: GrantFiled: January 18, 2005Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Mark Doczy, Lawrence D. Wong, Valery M. Dubin, Justin K. Brask, Jack Kavalieros, Suman Datta, Matthew V. Metz, Robert S. Chau
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Patent number: 7194642Abstract: Various embodiments are described to coordinate the servicing of multiple network interfaces.Type: GrantFiled: August 4, 2003Date of Patent: March 20, 2007Assignee: Intel CorporationInventor: Mark C. Pontarelli
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Patent number: 7194096Abstract: An input audio signal is analyzed to determine a power spectral density profile and the power spectral density profile is compared with at least one template profile. On the basis of the comparison, frequency bands of the input audio signal are selectively attenuated.Type: GrantFiled: June 25, 2003Date of Patent: March 20, 2007Assignee: Intel CorporationInventor: David L. Graumann
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Patent number: 7194131Abstract: An image capture system comprises an image input and processing unit. The image input obtains image information which is then passed to the processing unit. The processing unit is coupled to the image input for determining image metrics on the image information. The processing unit initiates a capture sequence when the image metrics meet a predetermined condition. The capture sequence may store one or more images, or it may indicate that one or more images have been detected. In one embodiment, the image input is a CMOS or CCD sensor.Type: GrantFiled: October 2, 2003Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Randy R. Dunton, Lawrence A. Booth, Jr.
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Patent number: 7193974Abstract: A method and apparatus for dynamically discovering alias domains is described. A method comprises dynamically discovering a set of subnets, the set of subnets having visibility of a transmission and selecting a network element to perform the transmission, the network element being in one of the set of subnets.Type: GrantFiled: August 10, 2001Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: David A. Eatough, Gregory P. Olsen
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Patent number: 7194661Abstract: An online system monitoring technique quickly and efficiently identifies failures or other system errors arising during operation of an intermediate network node, such as a network switch. The technique comprises Keep Alive Buffer packets/cells (“KABs”) that exercise data and control paths extending from every ingress port to every egress port in the switch. By exercising the data and control paths, the KABs enable testing of, and ensuring against, component failures, missing modules or other types of failure that can be detected as soon as possible, to thereby prevent data flow backup or other performance degradation in the switch.Type: GrantFiled: December 23, 2002Date of Patent: March 20, 2007Assignee: Intel CorporationInventor: Christopher J. Payson
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Patent number: 7194071Abstract: The exemplary embodiments of the present invention provide ECTF S.100-like functionality for H.248/Megaco-controlled media gateways and/or media servers by defining extensions to several of the H.248/Megaco ARFs, which are permissible within that protocol, to allow terminations within a media gateway more advanced media processing capabilities.Type: GrantFiled: December 28, 2000Date of Patent: March 20, 2007Assignee: Intel CorporationInventor: Paul A. Rupsis
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Patent number: 7191515Abstract: An electrical assembly (200, FIG. 2) is formed from two, interconnected circuit boards (202, 204). Conductive spacers (240) and a conductive material (260) are placed between complementary bond pads (218, 232) on the circuit boards. The conductive spacers are formed from a material that maintains its mechanical integrity during the process of attaching the circuit boards. The conductive material is a solder or conductive adhesive used to mechanically attach the circuit boards. In addition, an insulating material (270) is inserted into an interface region (250) between the circuit boards. The insulating material provides additional mechanical connection between the circuit boards. In one embodiment, one circuit board (202) includes a glass panel that holds an array of organic light emitting diodes (OLEDs), and the other circuit board (204) is a ceramic circuit board. Together, the interconnected circuit board assembly (200) forms a portion of a flat panel display (1102, FIG. 11).Type: GrantFiled: July 28, 2003Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Robert C. Sundahl, Kenneth Wong
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Patent number: 7194182Abstract: Various methods, apparatuses, and systems in which an alignment tool holds an optical fiber and an optical alignment component in place during induction soldering. The alignment tool has alignment adjustments for the optical fiber as well as the optical alignment component. An induction soldering station induction solders the optical fiber to the optical alignment component in order to secure the optical fiber to the optical alignment component.Type: GrantFiled: November 25, 2002Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Ron A. Hagen, Rickie Charles Lake
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Patent number: 7194387Abstract: A method and apparatus for determining the minimum zone for an array of features with a true position tolerance. In one embodiment, a target function is defined according to a deviation value of each of at least two features from an array of features having a maximum deviation between an actual position and a nominal position. Once defined, the target function is minimized to determine a rotation parameter, a horizontal translation parameter and a vertical translation parameter that provide a minimum target function value as a minimum of the maximum deviation for the array of features. In one embodiment, an inspection report may be generated for the array of features, including at least the minimum, maximum deviation value, as well as the rotation parameter, the horizontal translation parameter and the vertical translation parameter that provide the minimum target function value. Other embodiments are described and claimed.Type: GrantFiled: September 30, 2005Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Anatoly Filatov, Robert J. Guderian, Eugene Tuv
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Patent number: 7194643Abstract: In some embodiments, a method and apparatus for an energy efficient clustered micro-architecture are disclosed. In one embodiment, the method includes the computation of an energy delay2 product for each active instruction scheduler and one or more associated function blocks of a current architecture configuration over a predetermined period. Once the energy delay2 product is computed, the computed product is compared against an energy delay2 product calculated for a prior architecture configuration to determine an effectiveness of the current architecture configuration. Based on the effectiveness of the current architecture configuration, a number of active instruction schedulers and one or more associated functional blocks within the current architecture configuration is adjusted. In one embodiment, the number of active instruction schedulers and one or more associated functional blocks may be increased or decreased to improve power efficiency of the cluster micro-architecture.Type: GrantFiled: September 29, 2003Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Jose Gonzalez, Antonio Gonzalez
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Patent number: 7193901Abstract: A canary cell may be used in a semiconductor memory to indicate an incipient failure. For example, the canary cell may be provided on rows in a flash memory. Before a read disturb occurs, the canary cell may first sense the condition, for example, because it may be biased with a higher drain bias and is, therefore, more susceptible to the read disturb problem.Type: GrantFiled: April 13, 2005Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Paul Ruby, Sean Eilert
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Patent number: 7194597Abstract: A sharing mechanism is herein disclosed for multiple logical processors using a translation lookaside buffer (TLB) to translate virtual addresses, for example into physical addresses. The mechanism supports sharing of TLB entries among logical processors, which may access address spaces in common. The mechanism further supports private TLB entries among logical processors, which for example, may each access a different physical address through identical virtual addresses. The sharing mechanism provides for installation and updating of TLB entries as private entries or as shared entries transparently, without requiring special operating system support or modifications. Through use of the disclosed sharing mechanism, fast and efficient virtual address translation is provided without requiring more expensive functional redundancy.Type: GrantFiled: December 22, 2005Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Thomas E. Willis, Achmed R. Zahir
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Patent number: 7193994Abstract: A technique synchronizes a crossbar switch fabric of a network switch having a plurality of modules configured to transmit and receive data at high speeds. The crossbar switch fabric resides on a switch module and operates on fixed-size cells received at its input ports from line card modules over high-speed serial communication paths of the switch. To eliminate resynchronization between the modules after each serial communications path traversal, each module is allowed to operate within its own clock domain, thereby forcing the entire resynchronization task upon a receive data path of the switch module. Although this results in resynchronization of a “large magnitude”, the task only needs to be performed once and entirely on the switch module.Type: GrantFiled: August 16, 2002Date of Patent: March 20, 2007Assignee: Intel CorporationInventor: Christopher J. Payson
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Patent number: 7194157Abstract: An optical output coupler having a reflector integrated in an evanescent coupler. In one aspect of the present invention, an apparatus according to an embodiment of the present invention includes first and second optical paths. An optical beam is to be directed through the first optical path. The apparatus also includes an evanescent coupler, which evanescently couples the first and second optical paths. The apparatus further includes a reflector, which is included in the evanescent coupler and integrated in the first and second optical paths. The optical beam that is directed through the first optical path is reflected from the reflector as the optical beam is concurrently evanescently coupled from the first to the second optical path.Type: GrantFiled: January 9, 2006Date of Patent: March 20, 2007Assignee: Intel CorporationInventor: Richard Jones
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Patent number: 7192890Abstract: A dielectric deposited on a substrate may be exposed to a salt solution. While exposed to the salt solution, an oxide is deposited on the dielectric.Type: GrantFiled: October 29, 2003Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Ying Zhou, Matthew V. Metz, Justin K. Brask, John Burghard, Markus Kuhn, Suman Datta, Robert S. Chau
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Patent number: 7193427Abstract: A leakage inverter has a switching delay in one direction that is directly proportional to the drain or gate leakage current of either an n-type or p-type device. For one aspect, a leakage ring oscillator includes an odd number of inverters including at least one leakage inverter such that the frequency of oscillation of the leakage ring oscillator is directly proportional to local device leakage. For another aspect, a leakage ring oscillator may be used to indicate temperature and/or temperature variation on a die.Type: GrantFiled: March 31, 2004Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Marijan Persun, Samie B. Samaan
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Patent number: 7192703Abstract: The present methods, compositions and systems are concerned with biomolecule 130 detection, identification and/or quantification by rolling circle amplification (RCA) and Raman detection. In particular embodiments of the invention, the RCA is exponential RCA or linear RCA. In some embodiments of the invention, the Raman detection is SERS or SERRS. The circular DNA template 150, 210, 310 to be amplified may comprise one or more polythymidine 320 residues, resulting in amplification products 170, 230, 250, 330, 410 containing multiple polyadenylate 340, 420 residues. The polyadenylates 340, 420 may be directly detected by Raman detection. Alternatively, one or more Raman labels may be incorporated into the amplification products 170, 230, 250, 330, 410 to facilitate Raman detection.Type: GrantFiled: February 14, 2003Date of Patent: March 20, 2007Assignee: Intel Corporation, Inc.Inventors: Lei Sun, Xing Su
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Patent number: 7194671Abstract: An processor includes first and second execution cores that operate in an FRC mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The FRC check unit temporarily stores results from the first or second core, and a timer is activated if a mismatch is detected. If the error detector detects a recoverable error before the timer interval expires, a recovery routine is activated. If the timer interval expires first, a reset routine is activated.Type: GrantFiled: December 31, 2001Date of Patent: March 20, 2007Assignee: Intel CorporationInventors: Steven J. Tu, Alexander J. Honcharik, Hang T. Nguyen, Sujat Jamil, Quinn W. Merrell
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Patent number: 7191321Abstract: A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references.Type: GrantFiled: August 19, 2003Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Debra Bernstein, Donald F. Hooper, Matthew J. Adiletta, Gilbert Wolrich, William Wheeler
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Patent number: 7191353Abstract: A master device communicating a first range of speeds at which the master device is operable, to a first slave device, the master device and the first slave device determining a second range of speeds most closely matched to the first range of speeds at which each of the master device and the first slave device is respectively operable; and the master device setting the operating range of speeds of each of the master device and the first slave device to the second target range of speeds.Type: GrantFiled: March 31, 2003Date of Patent: March 13, 2007Assignee: Intel CorporationInventor: Laurance F. Wygant
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Patent number: 7190286Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.Type: GrantFiled: December 22, 2005Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Maged M. Ghoneima, Peter Caputa, Muhammad M. Khellah, Ram Krishnamurthy, James W. Tschanz, Yiben Ye, Vivek K. De, Yehea I. Ismail
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Patent number: 7191255Abstract: Transaction layer link down handling for Peripheral Component Interconnect (PCI) Express. A link between an input/output (I/O) controller port of an I/O controller and a device port of a device is initialized, wherein the link includes a physical layer, a data link layer, and a transaction layer. The transaction layer is restored after a data link down condition without software intervention.Type: GrantFiled: October 27, 2004Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Kar Leong Wong, Mikal C. Hunsaker, Prasanna C. Shah
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Patent number: 7189596Abstract: A method of fabricating microelectronic dice by providing or forming a first encapsulated die assembly and a second encapsulated die assembly. Each of the encapsulated die assemblies includes at least one microelectronic die disposed in a packaging material. Each of the encapsulated die assemblies has an active surface and a back surface. The encapsulated die assemblies are attached together in a back surface-to-back surface arrangement. Build-up layers are then formed on the active surfaces of the first and second encapsulated assemblies, preferably, simultaneously. Thereafter, the microelectronic dice are singulated, if required, and the microelectronic dice of the first encapsulated die assembly are separated from the microelectronic dice of the second encapsulated die assembly.Type: GrantFiled: September 14, 2000Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Chun Mu, Qing Ma, Quat Vu, Steven Towle
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Patent number: 7190374Abstract: Shading a polygon includes identifying points on edges of the polygon using shading values for vertices of the polygon, connecting the points to form at least two areas within the polygon, and shading the at least two areas differently. Vertices are assigned to at least two different bins. The bins correspond to different shades. The points may be identified by identifying points on edges of the polygon having vertices assigned to different bins.Type: GrantFiled: February 28, 2001Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Adam T. Lake, Carl S. Marshall, Marc S. Blackstein
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Patent number: 7191349Abstract: A method for a mechanism for processor power state aware distribution of lowest priority interrupts. The method of one embodiment comprises receiving first power state information from a first component and second power state information from a second component. First task priority information from the first component and second task priority from the second component are also received. An interrupt request from a first device for servicing is received. Power state and task priority information for the first and second components are evaluated to determine which component should service the interrupt request. Either the first component or the second component is selected to be a destination component to service the interrupt request based on the power state and task priority information. The interrupt request is communicated to the destination component.Type: GrantFiled: December 26, 2002Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Shivnandan D. Kaushik, John W. Horigan, Alon Naveh, James B. Crossland
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Patent number: 7189497Abstract: Multiple Bragg gratings are fabricated in a single planar lightwave circuit platform. The gratings have nominally identical grating spacing but different center wavelengths, which are produced using controlled photolithographic processes and/or controlled doping to control the effective refractive index of the gratings. The gratings may be spaced closer together than the height of the UV light pattern used to write the gratings.Type: GrantFiled: July 24, 2002Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Anders Grunnet-Jepsen, Alan E. Johnson, John N. Sweetser
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Patent number: 7190585Abstract: A heat spreader, comprising a metal body with attached standoffs located approximately above the integrated circuit, is described. The standoffs should improve bond layer thickness control between the integrated circuit and the heat spreader, leading to a lower cost and lower mass package, as well as a more reliable device with increased thermal performance.Type: GrantFiled: July 3, 2003Date of Patent: March 13, 2007Assignee: Intel CorporationInventor: Sabina J. Houle
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Patent number: 7191381Abstract: A method and medium tangibly embodying the method of constructing a lookup table of modes for encoding data for transmission in a wireless communication channel from a transmit unit to a receive unit by using at least one quality parameter of the data and its first-order and second-order statistical parameters to arrange the modes in the lookup table. The first-order and second-order statistical parameters can be determined from a simulation of the wireless communication channel or from field measurements of the wireless communication channel. The modes in the lookup table are ordered by a target value of a communication parameter such as PER, BER, data capacity, signal quality, spectral efficiency, throughput or another suitable communication parameter set to achieve a desired quality of service. The quality parameter selected is conveniently a short-term quality parameter such as signal-to-interference and noise ratio (SINR), signal-to-noise ratio (SNR) or power level.Type: GrantFiled: December 5, 2000Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: David J. Gesbert, Severine E. Catreux, Robert W. Heath, Jr.
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Patent number: 7191440Abstract: Transitions among schedulable entities executing in a computer system are tracked in computer hardware or in a virtual machine monitor. In one aspect, the schedulable entities are operating system processes and threads, virtual machines, and instruction streams executing on the hardware. In another aspect, the schedulable entities are processes or threads executing within the virtual machines under the control of the virtual machine monitor. The virtual machine monitor derives scheduling information from the transitions to enable a virtual machine system to guarantee adequate scheduling quality of service to real-time applications executing in virtual machines that contain both real-time and non-real-time applications. In still another aspect, a parent virtual machine monitor in a recursive virtualization system can use the scheduling information to schedule a child virtual machine monitor that controls multiple virtual machines.Type: GrantFiled: August 15, 2001Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Erik Cota-Robles, Sebastian Schoenberg, Stalinselvaraj Jeyasingh, Alain Kagi, Michael Kozuch, Gilbert Neiger, Richard Uhlig
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Patent number: 7188418Abstract: A heat sink for dissipating heat from an electronic component includes a core and a plurality of fins extending outwardly from the core. The fins may be at least partially curved. Each fin may split into a plurality of tines that extend away from the core.Type: GrantFiled: November 5, 2003Date of Patent: March 13, 2007Assignee: Intel CorporationInventor: Ketan R. Shah
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Patent number: 7190961Abstract: A device scans its range for newly-discovered devices in a mobile ad-hoc network. Upon detecting a newly-discovered device, the two devices arbitrate how to synchronize their internal clocks. The devices then re-synchronize on schedule to enable data transmission. The devices may dynamically rearbitrate synchronization. The network as a whole is an emergent property of the peer-to-peer relationships between pairs of devices.Type: GrantFiled: October 18, 2001Date of Patent: March 13, 2007Assignee: Intel CorporationInventor: Jeremy Burr
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Patent number: 7191295Abstract: In one embodiment of the present invention, a method includes sensing a first burst length of data equal to half of a sense width of a plurality of sense amplifiers of a memory, and sensing a second burst length of data equal to the half of the sense width during a latency while sensing the first burst length of data.Type: GrantFiled: June 30, 2003Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Shekoufeh Qawami, Chaitanya S. Rajguru
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Patent number: 7190788Abstract: The methods and apparatus described herein encrypt an unencrypted binary string using an encryption key and a varying-radix conversion method. The encryption key is used to parse the unencrypted binary string into unencrypted sub-strings. The varying-radix conversion method is used to transform the unencrypted sub-strings into encrypted sub-strings. The encrypted sub-strings may then be concatenated together to produce an encrypted binary string. In addition, the reverse process is employed to recover the unencrypted binary string from the encrypted binary string. For example, the decryption process may occur after the encrypted binary string is transmitted over a network communications system.Type: GrantFiled: September 13, 2002Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Rongzhen Yang, Zheng-Hua Zhou, Michael Zhang
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Patent number: 7191375Abstract: A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet for a request transaction to a receiving device. The receiving device checks for error conditions. If an error condition exists and if the packet for the request transaction indicates that a completion is not expected by the transmitting device, an error message is delivered by the receiving device to the transmitting device.Type: GrantFiled: December 28, 2001Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Gary Solomon, David Harriman, Jasmin Ajanovic
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Patent number: 7191281Abstract: A mobile computer system such as mobile PC operable between a normal, stationary mode and a Navigation mode for optimal system performance and power management for mobile applications.Type: GrantFiled: June 13, 2001Date of Patent: March 13, 2007Assignee: Intel CorporationInventor: Sundeep M. Bajikar
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Patent number: 7191453Abstract: A system of forming a bridge between non Java services and a Jini (™) interface. A non Java service is encapsulated using special code which makes it look like a Java service. Other aspects are also automatically formed. The Java service is automatically published with a broker such as a Jini (™) broker.Type: GrantFiled: November 30, 2000Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Krishnamurthy Srinivasan, Edala R. Narasimha
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Patent number: 7190667Abstract: Some embodiments of the present invention include data network comprising a host system having a host-fabric adapter; at least one remote system; a switch fabric which interconnects said host system via said host-fabric adapter to said remote system along different physical links for data communications; and at least one communication port provided in the host-fabric adapter of the host system including a set of transmit and receive buffers capable of sending and receiving data packets concurrently via respective transmitter and receiver at an end of a physical link, via the switched fabric, and a flow control mechanism utilized to prevent loss of data due to receive buffer overflow at the end of the physical link. Other embodiments are described and claims.Type: GrantFiled: April 26, 2001Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Dean S. Susnow, Richard D. Reohr, Jr.
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Patent number: 7190287Abstract: Embodiments of a method of generating Huffman code length information are disclosed. In one such embodiment, a data structure is employed, although, of course, the invention is not limited in scope to the particular embodiments disclosed.Type: GrantFiled: December 6, 2005Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Tinku Acharya, Ping-Sing Tsai
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Patent number: 7190931Abstract: A receiver is calibrated using a transmitter that can output a plurality of substantially constant amplitude signals.Type: GrantFiled: September 29, 2003Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Bryan K. Casper, Aaron K. Martin, James E. Jaussi, Stephen R. Mooney
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Patent number: 7191164Abstract: In one embodiment, the present invention includes a method to obtain a query image and search a database corresponding to object images for a solution set having a maximum similarity to the query image using fuzzy logic. Also in certain embodiments, based on fuzzy logic, the database may be partitioned into multiple sets based on a fuzzy similarity analysis of a measure of the object images to various thresholds.Type: GrantFiled: August 19, 2003Date of Patent: March 13, 2007Assignees: Intel Corporation, Indian Institute of TechnologyInventors: Ajoy K. Ray, Ranjit K. Mishra, Tinku Acharya
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Patent number: 7191433Abstract: The present application describes a compiler of a network packet classification programming language that generates code for processors such as an application processor and a processing engine. The programming language includes a variety of instructions including an instruction to declare a network protocol and an instruction to specify a rule and at least one action to perform if the rule applies. A processor executing instructions generated by the compiler assigns values based on instructions to declare a network protocol and applies the rule instructions to received packets. The programming language may also include other instructions such as an instruction to search a set of values and identify whether an encapsulated packet header is present in a packet.Type: GrantFiled: December 29, 2003Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Charles E. Narad, Kevin Fall, Neil MacAvoy, Pradip Shankar, Leonard M. Rand, Jerry J. Hall
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Patent number: 7190715Abstract: An asymmetric digital subscriber loop modem may achieve efficiency and cost reduction by providing a coder/decoder (codec) chip which transmits data externally of the chip when the data is at a reduced or lower data rate. That is, instead of transmitting the data at a higher data rate, which may result in increased cost, for example for EMI shielding, the codec chip transmits the data when the data is at a reduced data rate.Type: GrantFiled: December 23, 1999Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Michael J. McTague, Raman M. Srinivasan, Brad A. Barmore
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Patent number: 7190787Abstract: A stream cipher is provided with a first and a second data bit generators to generate in parallel a first and a second stream of data bits. The stream cipher is further provided with a combiner function having a shuffling unit including a storage structure to generate a pseudo random sequence, by combining the first stream of data bits with at least stochastically generated past values of the first streams of data bits, generated by using the second stream of data bits to stochastically operate the storage structure of the shuffle unit to memorize and reproduce the data bits of the first stream.Type: GrantFiled: November 30, 1999Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Gary L. Graunke, Carl M. Ellison
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Patent number: 7190883Abstract: In some embodiments, the invention includes a method of processing a video stream. The method involves detecting a request to playback a particular frame. It is determined whether a decoded version of the particular frame is in a decoded frame cache. If it is not, the method includes(i) determining a frame dependency for the particular frame; (ii) determining which of the frames in the frame dependency are in the decoded frame cache; (iii) decoding any frame in the frame dependency that is not in the decoded frame cache and placing it in the decoded frame cache; and (iv) using at least some of the decoded frames in the frame dependency to decode the particular frame to create a decoded version of the particular frame. In some embodiments, the request to playback a particular frame is part of a request to perform frame-by-frame backward playback and the method is performed for successively earlier frames with respect to the particular frame as part of the frame-by-frame backward playback.Type: GrantFiled: June 18, 1999Date of Patent: March 13, 2007Assignee: Intel CorporationInventor: Boon-Lock Yeo
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Patent number: 7190068Abstract: Embodiments of the invention provide a microelectronic device having a heat spreader positioned between a chip and substrate to which the chip is electrically connected. For one embodiment of the invention, the heat spreader is a thermal slug having a coefficient of thermal expansion approximately equal to the coefficient of thermal expansion of the chip.Type: GrantFiled: June 25, 2004Date of Patent: March 13, 2007Assignee: Intel CorporationInventors: Dale Hackitt, Robert Nickerson, Brian Taggart