Intel Patents
Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.
Intel Patents by Type- Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
- Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
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Patent number: 7178034Abstract: A method and apparatus for strong authentication and proximity-based access retention is presented. In this regard, an authentication agent is introduced to securely communicate with a key device associated with a user to identify the user, retrieve credentials for the user, securely communicate a session key to the key device, and identify the user who is requesting access to target resource(s) based on the user's credentials while the user's key device is proximate to the target resource(s).Type: GrantFiled: December 31, 2002Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Joseph F. Cihula, Baiju V. Patel
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Patent number: 7175680Abstract: Methods and solutions for forming self assembled organic monolayers that are covalently bound to metal interfaces are presented along with a device containing a self assembled organic monolayer. Embodiments of the present invention utilize self assembled thiolate monolayers to prevent the electromigration and surface diffusion of copper atoms while minimizing the resistance of the interconnect lines. Self assembled thiolate monolayers are used to cap the copper interconnect lines and chemically hold the copper atoms at the top of the lines in place, thus preventing surface diffusion. The use of self assembled thiolate monolayers minimizes the resistance of copper interconnect lines because only a single monolayer of approximately 10 ? and 20 ? in thickness is used.Type: GrantFiled: November 23, 2004Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: David H. Gracias
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Patent number: 7178054Abstract: A method according to one embodiment may include receiving a frame, determining a frame type of the frame, accessing a location of memory associated with the frame type, the location comprising at least one programmable data element, and checking a validity of the frame in response to data in the location of memory associated with the frame type. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.Type: GrantFiled: February 9, 2004Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Pak-Lung Seto, Devicharan Devidas
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Patent number: 7177142Abstract: The apparatus and method described herein are for coupling an integrated circuit to a circuit board, while eliminating the need for a backing plate, when a compression socket is utilized. A plurality of tension pins are coupled to an integrated circuit for engaging a plurality of corresponding barrels in a circuit board to compress a compression socket to make an electrical connection between the integrated circuit and the circuit board.Type: GrantFiled: September 29, 2004Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Ashok N. Kabadi, Frank R. DeWeese
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Patent number: 7177186Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.Type: GrantFiled: March 28, 2006Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Daniel R. Elmhurst, Karthikeyan Ramamurthi, Quan H. Ngo, Robert L. Melcher
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Patent number: 7176090Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.Type: GrantFiled: September 7, 2004Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Brian S. Doyle, Robert S. Chau
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Patent number: 7178056Abstract: Application software on a fault tolerant system having an active engine and a standby engine is upgraded. As part of the upgrade, the system determines if the active engine and the standby engine are executing different versions of the application software. The system sends a description of work units from the active engine to the standby engine and sends database activities from the active engine to the standby engine.Type: GrantFiled: December 4, 2001Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Vedvyas Shanbhogue
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Patent number: 7176751Abstract: A trimmable voltage reference uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The threshold voltage of the flash cell can be programmed to affect the reference voltage.Type: GrantFiled: November 30, 2004Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Hari Giduturi, Kerry D. Tedrow
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Patent number: 7176842Abstract: A slot antenna having one or more electronic components attached across a slot of the antenna to provide either an RF open or an RF short based on the bias supplied to a control terminal of the electronic component. The antenna is tunable via the RF open or short across the slot.Type: GrantFiled: October 27, 2004Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Allen W. Bettner, Xintian E. Lin, Alan E. Waltho
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Patent number: 7178045Abstract: A transmitting device and a receiving device are coupled together via an interconnect. An electrical idle ordered set is received at the receiving device power management unit after having been transmitted by the transmitting device and received at the input pins of the receiving device and moving through the receiver logic pipeline. At the time the electrical idle ordered set has been recognized at the end of the receiver logic pipeline, the power management unit checks for activity on the interconnect. If there is no activity on the interconnect, then the power management unit causes the receiving device to enter a low power state where the receiver circuitry (input buffers) is turned off. If there is activity on the interconnect when the electrical idle ordered set is received at the power management unit, then the power management unit does not cause the receiver circuitry to be turned off.Type: GrantFiled: December 30, 2003Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: David M. Puffer, Suneel G. Mitbander, Sarath K. Kotamreddy
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Patent number: 7177288Abstract: A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.Type: GrantFiled: November 28, 2001Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Stephen R. Mooney, Aaron K. Martin, Matthew B. Haycock, Bryan K. Casper, Shekhar Y. Borkar, Joseph T. Kennedy, James E. Jaussi
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Patent number: 7177967Abstract: In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.Type: GrantFiled: September 30, 2003Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Stalinselvaraj Jeyasingh, Andrew V. Anderson, Steven M. Bennett, Erik Cota-Robles, Alain Kagi, Gilbert Neiger, Richard Uhlig
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Patent number: 7177205Abstract: In some embodiments, a chip includes a chip interface to accept a delay control signal from outside the chip. The chip also includes a controllable delay line to delay an input signal responsive to the delay control signal to provide an output signal with a particular phase relationship to the input signal. Other embodiments are described and claimed.Type: GrantFiled: April 27, 2004Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Joseph T. Kennedy, Stephen R. Mooney
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Patent number: 7178009Abstract: A digital signal processor may include a plurality of processing elements that are coupled together to accomplish a specialized function. Each processing element may utilize the same shared storage in a form of a plurality of general purpose registers. Each of these registers may be accessed by any of the processing elements. Each register may include a data storage section and a plurality of storage areas for data valid bits that indicate whether the data is valid or not for each of the plurality of processing elements.Type: GrantFiled: April 4, 2001Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: David K. Vavro
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Patent number: 7177211Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a host-side memory channel port and a downstream memory channel port, allowing multiple modules to be chained point-to-point. In the present disclosure, a separate bus, such as a low-speed system management bus, connects to a memory module buffer. In response to commands received over the system management bus, the memory module can initiate commands and transmit those commands over its downstream memory channel port as if the commands originated from a host connected to the host-side memory channel port. This functionality allows module-to-module memory channels and memory modules to be tested independent of a host memory controller and host memory channel. Other embodiments are described and claimed.Type: GrantFiled: November 13, 2003Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: David Zimmerman
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Patent number: 7177502Abstract: A thermo-optical device may use a heater to tune an optical device such as an optical switch, a Mach-Zehnder interferometer, or a variable optical attenuator, to mention a few examples. In some embodiments, polarization-dependent losses caused by the heating and power efficiency may be improved by defining a clad core including an optical core and cladding material on a substrate and covering the clad core on three sides with a heater.Type: GrantFiled: June 13, 2005Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Tsung-Ein Tsai, Junnarker Mahesh, Gabel Chong
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Patent number: 7177594Abstract: A mobile ad hoc network may be established between a plurality of devices that have common contacts on their contact lists. The contact lists may be conventional contacts stored in a list of contacts on a scheduling and information management or other software packages in one embodiment. Communications with various devices is limited to those devices listed on the list of contacts. Modification of those lists of contacts is controlled on a password-protected basis in one embodiment. Thus, a parent, for example, may limit the ability of child users to contact or be contacted by and communicate with unauthorized persons.Type: GrantFiled: September 6, 2001Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Jeremy Burr
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Patent number: 7176575Abstract: An electronic device includes a material having a first dielectric constant (K) value, and a material having a second dielectric constant (K) value. The first dielectric constant (K) value is lower than the second dielectric constant (K) value. The electronic device also includes input/output connection conductors for transmitting signals to and from a die. The input/output connection conductors are routed through the material of the interposer having the first dielectric constant. The electronic device also includes power connection conductors for delivering power to the die, and ground connection conductors. The power and ground connection conductors are routed through the material having the second dielectric constant.Type: GrantFiled: September 30, 2004Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Larry E. Mosley, Cengiz A. Palanduz, Victor Prokofiev
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Patent number: 7177189Abstract: According to some embodiments, a memory device having multiple memory units includes one or more redundant memory units. Upon detection of an electrical characteristic indicating a failing memory unit, one of the redundant memory units is used to replace the failing memory unit. Detection of failing memory units may be via current, voltage and/or resistance monitoring. If the electrical characteristic monitored exceeds a predetermined threshold, a memory unit is considered failing. The failing memory unit is removed from further use. The redundant memory unit is programmed to be accessible at the memory address of the removed memory unit. Replacement occurs automatically (that is, without user intervention).Type: GrantFiled: March 1, 2004Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Reed A. Linde, Alec W. Smidt
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Patent number: 7177176Abstract: In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).Type: GrantFiled: June 30, 2004Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Bo Zheng, Kevin Zhang, Fatih Hamzaoglu, Yih (Eric) Wang
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Patent number: 7177410Abstract: A residential phone system allows for local control of call features from any phone extension. The phone system may include a microcontroller that communicates along the phone lines at a non-utilized frequency to several extension phones in a residence. The microcontroller permits each phone to control call features such as call waiting, conference calling, paging, or other features. A control box may be included at any or all of the extension phones to provide a convenient user interface to access the call features.Type: GrantFiled: April 19, 2005Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Edward O. Clapper, Kevin P. Gambil
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Patent number: 7175510Abstract: A method and apparatus for polishing a thin film on a semiconductor substrate is described. A polishing pad is rotated and a wafer to be polished is placed on the rotating polishing pad. The polishing pad has grooves that channels slurry between the wafer and polishing pad and rids excess material from the wafer, allowing an efficient polishing of the surface of the wafer. The polishing pad smoothes out due to the polishing of the wafer and must be conditioned to restore effectiveness. A conditioning assembly with a plurality of diamonds is provided. The diamonds have predetermined angles that provide strength to the diamond. This allows for an optimal rotation speed and downward force in effective conditioning of the polishing pad, while reducing diamond fracture rate.Type: GrantFiled: April 19, 2005Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Randy S. Skocypec, Adam P. La Bell, Wade R. Whisler
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Patent number: 7177778Abstract: Provided is a method and system for managing data processing rates at a network adapter using a temperature sensor. A temperature of a component in the adapter transmitting data over a network is measured. A rate at which data is processed in the adapter over the network is reduced in response to determining that the measured temperature exceeds a threshold.Type: GrantFiled: November 30, 2004Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Daniel R. Gaur, Patrick L. Connor, Scott P. Dubal
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Patent number: 7177637Abstract: A method and/or apparatus to permit non-authorized wireless mobile devices access to public domain services of a local area network. One embodiment of the invention provides a wireless access point device, with a wireless port and a wired network port, with at least two modes of operation to permit authorized mobile devices access to network services and non-authorized mobile devices access to a particular set of network services. A list of free and/or pay-per-use network services is provided to non-authorized mobile devices to select the desired service(s). For pay-per-use services, a mobile device user can provide a form of payment for validation.Type: GrantFiled: March 1, 2002Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Jiewen Liu, Shahrnaz Azizi
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Patent number: 7177913Abstract: Disclosed is a method, system, and program for adding an operation (e.g., an operation that provides information about data for transfer or a storage operation) to a structure (e.g., a queue). If a priority level associated with a data packet identified by the operation has a first designation comprising a high priority, placing the operation into a first structure (e.g., a queue) with a least number of operations. If the priority level associated with the data packet identified by the operation has a second designation comprising a low priority, placing the operation into a second structure (e.g., a queue) with a most number of operations.Type: GrantFiled: December 5, 2002Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Patrick L. Connor
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Patent number: 7177888Abstract: A method of producing a uniform duty cycle output from a random bit source. The method includes testing the duty cycle of said random bit source; varying the output voltage of a voltage source if the duty cycle is not substantially fifty percent; and iteratively altering the output voltage of the voltage source until said duty cycle is substantially fifty percent.Type: GrantFiled: August 1, 2003Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Steven E. Wells
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Patent number: 7175970Abstract: In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.Type: GrantFiled: November 22, 2005Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Jun He, Jihperng Leu
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Patent number: 7177861Abstract: A method and system is provided for detecting occurrences of semantic temporal events based on observations extracted from input data and event models. The input data is fed into the system from some data source. Based on specified event to be detected, multiple-layer models corresponding to the event are retrieved. The models are used to determine the types of temporal observations to be extracted from the input data. The extracted temporal observations are then used, in combination with the multiple-layer models of the event, to detect the occurrences of the event.Type: GrantFiled: November 14, 2003Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Vasanth R. Tovinkere, Eugene Epshteyn, Richard J. Qian
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Patent number: 7176075Abstract: The present invention is a novel field effect transistor having a channel region formed from a narrow bandgap semiconductor film formed on an insulating substrate. A gate dielectric layer is formed on the narrow bandgap semiconductor film. A gate electrode is then formed on the gate dielectric. A pair of source/drain regions formed from a wide bandgap semiconductor film or a metal is formed on opposite sides of the gate electrode and adjacent to the low bandgap semiconductor film.Type: GrantFiled: January 6, 2005Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Robert S. Chau, Doulgas Barlage, Been-Yih Jin
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Patent number: 7177323Abstract: A multi-media call application is disclosed. The application guarantees quality of service (QOS) for a packet based multi-media call (CALL). The guaranty is effectuated through call associated individual media stream bandwidth control.Type: GrantFiled: March 13, 1998Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Rajendra S. Yavatkar, James E. Toga
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Patent number: 7176422Abstract: A heater for flip chip bonding transfers more heat to the periphery of a die than to the center. This may result in a more even temperature profile along the die and may help prevent epoxy voiding problems.Type: GrantFiled: June 17, 2005Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Song-Hua Shi
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Patent number: 7177983Abstract: In a Constant Access Time Bounded (CATB) cache, if a dirty line in a search group of the cache is selected for eviction from the cache, marking the dirty line as evicted, selecting a replacement line from a reserve, and inserting the replacement line into the search group.Type: GrantFiled: August 12, 2003Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Robert J. Royer
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Patent number: 7176565Abstract: A multilayer capacitor comprises separate terminals on at least three sides, and on as many as six sides. The capacitor can be fabricated in a large number of different configurations, types, and sizes, depending upon the target application. The separate terminals that are disposed on different sides of the capacitor can be readily coupled to a variety of different adjacent conductors, such as die terminals (including bumpless terminals or bars), IC package terminals (including pads or bars), and the terminals of adjacent discrete components. Methods of fabrication, as well as application of the capacitor to an electronic assembly, are also described.Type: GrantFiled: December 3, 2001Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Yuan-Liang Li, David G. Figueroa, Chee-Yee Chung
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Patent number: 7177301Abstract: A method of constructing a permuting network. A configuration for layers of a permuting network is selected based on a set of integer factors of N, the number of signals to be permuted, and on pre-selected types of switches. The permuting network is constructed in layers by using the pre-selected types of switches based on the selected configuration.Type: GrantFiled: December 27, 2001Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Michael D. Ruehle
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Patent number: 7176863Abstract: A flat panel display is described having a matrix of liquid crystals, wherein the liquid crystals have a common node. A pair of voltages that are applied to the common node help determine the rms voltages that are applied to the liquid crystals. The pair of voltages are tailored to bring a maximum rms voltage that is applied to the liquid crystals so as to fall along the lower knee of a transmittance vs. rms voltage curve that characterizes the performance of the liquid crystals.Type: GrantFiled: April 23, 2002Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Don Nguyen
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Patent number: 7177293Abstract: A telecommunications system supports a variety of packet data services with throughputs ranging from low to high data rates. The system controls the user data transmission over a channel according to the user data throughput requirements of the application. By properly scheduling the time that particular transmission takes place, high data rate applications may be supported without the need for code aggregation, and low rate users may be supported without the requirement of multiple spreading factors. Base stations may transmit scheduling information to user devices in downlink time slots and user devices may transmit status information to base stations in uplink time slots.Type: GrantFiled: April 30, 2002Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Carl Mansfield
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Patent number: 7177270Abstract: Large payload files are selectively partitioned in blocks and the blocks distributed to a plurality of distribution stations at the edge of the network qualified to have the data. Each qualified station decides how much and what portion of the content to save locally, based on information such as network location and environment, usage, popularity, and other distribution criteria defined by the content provider. Different pieces of a large payload file may be available from different nodes, however, when a user requests access to the large payload file, for example, through an application server, a virtual file control system creates an illusion that the entire file is present at the connected node. However, since only selective portions of the large payload file may actually be resident at that node's storage at the time of request, a cluster of distribution servers at the distribution station may download the non-resident portions of the file as the application server is servicing the user.Type: GrantFiled: May 18, 2001Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Siew Yong Sim, Desmond Cho-Hung Chan
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Patent number: 7176122Abstract: A polymer dielectric material includes a sidewall passivating layer on the opposing sidewall surfaces of an opening in the dielectric layer for a via or trench. The sidewall passivating layer may be deposited on the sidewall surfaces, as well as the bottom surface of an opening having a first depth in the polymer dielectric layer. After the sidewall passivating layer is added, the depth of the opening may be increased to a second depth. The sidewall passivating layer provides a barrier to removal of the polymer dielectric from the sidewalls, preventing or reducing undercutting below a hard mask.Type: GrantFiled: March 4, 2003Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Hyun-Mog Park
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Patent number: 7177973Abstract: Methods and apparatuses are described for improving information transfer over a universal serial bus (USB). In some embodiments, an apparatus includes a USB-compliant near-end link and control logic coupled with the USB-compliant near-end link. The control logic may translate a USB-compliant reflective signal received from a USB host to a terminated signal. Other embodiments are described and claimed.Type: GrantFiled: July 1, 2005Date of Patent: February 13, 2007Assignee: Intel CorporationInventor: Daniel Kelvin Jackson
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Patent number: 7177971Abstract: An enhanced general input/output communication architecture, protocol and related methods are presented.Type: GrantFiled: August 22, 2002Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Jasmin Ajanovic, Hong Jiang, David Harriman
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Publication number: 20070032025Abstract: The present invention discloses a method for forming germanides on substrates with exposed germanium and exposed dielectric(s) topography, thereby allowing for variations in the germanide forming process. The method comprises the steps of depositing nickel on a substrate having topography, performing a first thermal step to convert substantially all deposited nickel in regions away from the topography into a germanide, selectively removing the unreacted nickel, and performing a second thermal step to lower the resistance of formed germanide.Type: ApplicationFiled: September 8, 2006Publication date: February 8, 2007Applicants: Interuniversitair Microelektronica Centrum (IMEC), Intel Corporation (INTEL), Katholieke Universiteit Leuven (KUL)Inventors: David Brunco, Karl Opsomer, Brice De Jaeger
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Patent number: 7171743Abstract: An apparatus and method for warpage compensation of a display panel substrate assembly are described. A method and apparatus for warpage compensation of a display panel substrate assembly are described. In one embodiment, the method includes the selection of a substrate having a substrate warpage level exceeding a warpage tolerance level. Once selected, a plurality of conductive bumps are formed over an area of the selected substrate. Once formed, a thermal process is applied to the plurality of conductive bumps to obtain a virtual plane over the area of the selected substrate have a coplanarity level below a coplanarity specification level. As such, utilizing embodiments of the present invention, lower cost substrates with substandard warpage levels may be utilized to form OLED panel substrate assemblies when compensated utilizing embodiments of the present invention.Type: GrantFiled: May 7, 2004Date of Patent: February 6, 2007Assignee: Intel CorporationInventor: Kenzo Ishida
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Patent number: 7174416Abstract: Methods of allocating, writing, reading, de-allocating, re-allocating, and reclaiming space within a nonvolatile memory having a bifurcated storage architecture are described. A method of reliably re-allocating a first object includes the step of storing a location of a first object in a first data structure. A location of the first data structure is stored in a second data structure. A duplicate of the first object is formed by initiating a copy of the first object. An erase of the first object is initiated. A write of a second object to the location of the first object is then initiated. The duplicate object is invalidated. The status of copying, erasing, and writing is tracked. The copy status, erase status, write status, and a restoration status are used to determine a recovery state upon initialization of the nonvolatile memory. The duplicate object is invalidated, if the writing status indicates that the writing of the second object has been completed.Type: GrantFiled: September 2, 2003Date of Patent: February 6, 2007Assignee: Intel CorporationInventors: Robert N. Hasbun, David A. Edwards, Andrew H. Gafken, Christopher J. Spiegel
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Patent number: 7173639Abstract: A pulse width modulation driven display such as a spatial light modulator, which updates pixel data between PWM periods of consecutive frames, to avoid tearing artifacts in the perceived display image.Type: GrantFiled: April 10, 2002Date of Patent: February 6, 2007Assignee: Intel CorporationInventor: Samson Huang
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Patent number: 7174060Abstract: A method and apparatus that includes a first waveguide segment that differentially changes the amplitude of the light relative to a first polarization orientation, a thickness of oriented liquid crystal or other birefringent material sufficient to delay one polarization component one-half wavelength relative to another, and a second waveguide segment that also differentially changes the amplitude of the light based on the polarization orientation. Also, an apparatus that includes a thin polarization converter that includes a thin first substrate that is substantially transparent to a wavelength of light, and a birefringent material deposited on one or more surfaces of the first substrate and oriented such that the polarization converter forms a half-wavelength birefringent plate for the light. Also, an apparatus having a first substrate surface, a second substrate surface, and a liquid crystal material between the first and second substrate surfaces to form a polarization converter.Type: GrantFiled: July 26, 2005Date of Patent: February 6, 2007Assignee: Intel CorporationInventors: Nagesh K. Vodrahalli, Achintya K. Bhowmik, Connie C. Liu, Takaharu Fujiyama, Kenji Takahashi, Biswajit Sur
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Patent number: 7174566Abstract: Intrusion preludes may be detected (including detection using fabricated responses to blocked network requests), and particular sources of network communications may be singled out for greater scrutiny, by performing intrusion analysis on packets blocked by a firewall. An integrated intrusion detection system uses an end-node firewall that is dynamically controlled using invoked-application information and a network policy. The system may use various alert levels to trigger heightened monitoring states, alerts sent to a security operation center, and/or logging of network activity for later forensic analysis. The system may monitor network traffic to block traffic that violates the network policy, monitor blocked traffic to detect an intrusion prelude, and monitor traffic from a potential intruder when an intrusion prelude is detected.Type: GrantFiled: February 1, 2002Date of Patent: February 6, 2007Assignee: Intel CorporationInventor: Satyendra Yadav
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Patent number: 7173803Abstract: An inter-digital capacitor may be used in a power socket for a microelectronic device. In one embodiment an integrated, low-resistance power and ground terminal configuration is disclosed. The capacitor plates are alternatively coupled to the power and ground terminals. Two polarity types are disclosed. A method of operation is also described.Type: GrantFiled: May 3, 2004Date of Patent: February 6, 2007Assignee: Intel CorporationInventors: Dong Zhong, Jiangqi He, Yuan-Liang Li
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Patent number: 7174451Abstract: A system and method to resume execution of a client system from a saved system state without executing a boot-up process. A data storage unit and the client system having volatile system memory are coupled to a network. Data stored on the data storage unit is received via the network and loaded into the volatile system memory of the client system. The data contains information for the client system to resume execution from the saved system state without executing a boot-up process after a power-off state. The client system is then capable of resuming operation from the saved system state.Type: GrantFiled: March 31, 2003Date of Patent: February 6, 2007Assignee: Intel CorporationInventors: Vincent J. Zimmer, Michael A. Rothman, Mallik Bulusu
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Patent number: 7173329Abstract: Arrangements are used to supply power to a semiconductor package.Type: GrantFiled: September 28, 2001Date of Patent: February 6, 2007Assignee: Intel CorporationInventors: Kristopher Frutschy, Chee-Yee Chung, Bob Sankman
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Patent number: 7174462Abstract: Authenticating a user operating an un-trusted access device includes causing the display, on the un-trusted access device, of a plurality of photographs to the user, at least one of the photographs being from the user's personal photograph collection and already familiar to the user, remaining photographs being decoy photographs, accepting an input selection from the user identifying one of the displayed photographs, and allowing access when the user's selection correctly identifies a sequence of displayed photographs from the user's photograph collection. No user training prior to using the authentication system is needed and no pre-selection of a password or photograph is necessary.Type: GrantFiled: November 12, 2002Date of Patent: February 6, 2007Assignee: Intel CorporationInventors: Trevor A. Pering, John J. Light, Roy Want, Muralidharan Sundararajan