Intel Patents

Intel Corporation designs and manufactures microprocessors and chipsets for computing and communications equipment manufacturers. Its products may be found in desktops, servers, tablets, smartphones and other devices.

Intel Patents by Type
  • Intel Patents Granted: Intel patents that have been granted by the United States Patent and Trademark Office (USPTO).
  • Intel Patent Applications: Intel patent applications that are pending before the United States Patent and Trademark Office (USPTO).
  • Devices and methods for priority frequency band derivation in wireless communications
    Patent number: 11178672
    Abstract: A method and device for determining one or more frequency bands to report to a network, including acquiring an information from the network, assembling a database, the database comprising a plurality of frequency bands derived from the information acquired from the network, creating a priority frequency band list using an extraction parameter, wherein the priority frequency band list consists of one or more frequency bands from the plurality of frequency bands in the database, and reporting the priority frequency band list to the network.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventor: Yucheng Dai
  • Apparatus, system and method of communication during a transmit opportunity (TXOP)
    Patent number: 11178570
    Abstract: For example, a first STA may be configured to transmit to a second STA a message including a first value to indicate an available memory size at the first STA at a beginning of a TXOP, and a second value to indicate a maximal length of an A-MPDU transmission during the TXOP; to receive an initial A-MPDU from the second STA during the TXOP, a length of the initial A-MPDU is not longer than the first value; to determine a capacity value based on a current available memory size at the first STA, the capacity value to indicate whether the second STA is to be allowed to send to the first STA a subsequent A-MPDU having a length which is not longer than the second value; and to transmit to the second STA an Ack including a buffer capacity field including the capacity value.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: November 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Oren Kedem, Ran Mor, Nir Paz, Alon Pais, Dror Markovich, Igor Brainman
  • Remote hardware acceleration
    Patent number: 11178063
    Abstract: A host fabric interface (HFI) apparatus, including: an HFI to communicatively couple to a fabric; and a remote hardware acceleration (RHA) engine to: query an orchestrator via the fabric to identify a remote resource having an accelerator; and send a remote accelerator request to the remote resource via the fabric.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Kshitij A. Doshi, Mark A. Schmisseur, Narayan Ranganathan, John Chun Kwok Leung
  • Efficient rotate adder for implementing cryptographic basic operations
    Patent number: 11176278
    Abstract: Integrated circuits to compute a result of summing m values, rotating the sum by k bits, and adding a summation of n values Bi to Bn to the rotated sum. An embodiment includes: a first carry save adder to add up the m values to generate a first carry and a first sum; rotator circuitry to rotate both the first carry and the first sum by k bits to generate a second carry and a second sum; a second carry save adder to add up the second carry, the second sum, and the summation of values Bi to Bn to generate a third carry and a third sum; two parallel adders to generate a first intermediate result and a second intermediary result based on the third carry and the third sum; and a multiplexer to generate the result utilizing various portions of the first and second intermediate results.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Amit Gradstein, Simon Rubanovich, Regev Shemy, Onkar P Desai, Jose Yallouz
  • Mechanisms for refractive index tuning semiconductor photonic devices
    Patent number: 11175451
    Abstract: Embodiments include apparatuses, methods, and systems including a semiconductor photonic device having a waveguide disposed above a substrate. The waveguide has a first section including amorphous silicon with a first refractive index, and a second section including crystalline silicon with a second refractive index different from the first refractive index. The semiconductor photonic device further includes a heat element at a vicinity of the first section of the waveguide. The heat element is arranged to generate heat to transform the amorphous silicon of the first section of the waveguide to partially or completely crystallized crystalline silicon with a third refractive index. The amorphous silicon in the first section may be formed with silicon lattice defects caused by an element implanted into the first section. Other embodiments may also be described and claimed.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Hasitha Jayatilleka, Harel Frish, Ranjeet Kumar, Haisheng Rong, John Heck
  • Bridged micro louvers for active privacy screen
    Patent number: 11175529
    Abstract: Disclosed herein are techniques related to privacy at display devices. The techniques include an apparatus having an electroactive privacy layer of a display device. The electroactive privacy layer is configured to restrict a propagation direction of light emission associated with a display layer of the display device. The restriction of propagation is generated by micro louvers formed in the electroactive privacy layer.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: November 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Thomas A. Nugraha, Dong Yeung Kwak, Jue Li, Chieko Uemizu
  • Advanced artificial intelligence agent for modeling physical interactions
    Patent number: 11176632
    Abstract: Described herein are advanced artificial intelligence agents for modeling physical interactions. An apparatus to provide an active artificial intelligence (AI) agent includes at least one database to store physical interaction data and compute cluster coupled to the at least one database. The compute cluster automatically obtains physical interaction data from a data collection module without manual interaction, stores the physical interaction data in the at least one database, and automatically trains diverse sets of machine learning program units to simulate physical interactions with each individual program unit having a different model based on the applied physical interaction data.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Anbang Yao, Dongqi Cai, Libin Wang, Lin Xu, Ping Hu, Shandong Wang, Wenhua Cheng, Yiwen Guo, Liu Yang, Yuqing Hou, Zhou Su
  • Systems and methods to perform floating-point addition with selected rounding
    Patent number: 11175891
    Abstract: Disclosed embodiments relate to performing floating-point addition with selected rounding. In one example, a processor includes circuitry to decode and execute an instruction specifying locations of first and second floating-point (FP) sources, and an opcode indicating the processor is to: bring the FP sources into alignment by shifting a mantissa of the smaller source FP operand to the right by a difference between their exponents, generating rounding controls based on any bits that escape; simultaneously generate a sum of the FP sources and of the FP sources plus one, the sums having a fuzzy-Jbit format having an additional Jbit into which a carry-out, if any, select one of the sums based on the rounding controls, and generate a result comprising a mantissa-wide number of most-significant bits of the selected sum, starting with the most significant non-zero Jbit.
    Type: Grant
    Filed: March 30, 2019
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Simon Rubanovich, Amit Gradstein, Zeev Sperber, Mrinmay Dutta
  • Transistor structures having multiple threshold voltage channel materials
    Patent number: 11177255
    Abstract: Embodiments include a first nanowire transistor having a first source and a first drain with a first channel in between, where the first channel includes a first III-V alloy. A first gate stack is around the first channel, where a portion of the first gate stack is between the first channel and a substrate. The first gate stack includes a gate electrode metal in contact with a gate dielectric. A second nanowire transistor is on the substrate, having a second source and a second drain with a second channel therebetween, the second channel including a second III-V alloy. A second gate stack is around the second channel, where an intervening material is between the second gate stack and the substrate, the intervening material including a third III-V alloy. The second gate stack includes the gate electrode metal in contact with the gate dielectric.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Sean T. Ma, Willy Rachmady, Gilbert Dewey, Matthew V. Metz, Harold W. Kennel, Cheng-Ying Huang, Jack T. Kavalieros, Anand S. Murthy, Tahir Ghani
  • System, apparatus and method for page granular,software controlled multiple key memory encryption
    Patent number: 11176059
    Abstract: In one embodiment, an apparatus comprises a processor to read a data line from memory in response to a read request from a VM. The data line comprises encrypted memory data. The apparatus also comprises a memory encryption circuit in the processor. The memory encryption circuit is to use an address of the read request to select an entry from a P2K table; obtain a key identifier from the selected entry of the P2K table; use the key identifier to select a key for the read request; and use the selected key to decrypt the encrypted memory data into decrypted memory data. The processor is further to make the decrypted memory data available to the VM. The P2K table comprises multiple entries, each comprising (a) a key identifier for a page of memory and (b) an encrypted address for that page of memory. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: David M. Durham, Siddhartha Chhabra, Amy L. Santoni, Gilbert Neiger, Barry E. Huntley, Hormuzd M. Khosravi, Baiju V. Patel, Ravi L. Sahita, Gideon Gerzon, Ido Ouziel, Ioannis T. Schoinas, Rajesh M. Sankaran
  • Packet processing with reduced latency
    Patent number: 11178076
    Abstract: Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Eliezer Tamir, Jesse C. Brandeburg, Anil Vasudevan
  • Micro light-emitting diode display fabrication and assembly
    Patent number: 11177243
    Abstract: Micro light-emitting diode (LED) display fabrication and assembly are described. In an example, a micro-light emitting diode (LED) display panel includes a display backplane substrate having a plurality of metal bumps thereon. A plurality of LED pixel elements includes ones of LED pixel elements bonded to corresponding ones of the plurality of metal bumps of display backplane substrate. One or more of the plurality of LED pixel elements has a graphene layer thereon. The graphene layer is on a side of the one or more of the plurality of LED pixel elements opposite the side of the metal bumps.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Anup Pancholi
  • Aggregated analytics for intelligent transportation systems
    Patent number: 11176815
    Abstract: Various systems and methods for collecting and generating analytics of data from motor vehicle safety and operation systems are disclosed herein. In one example, various minor vehicle incidents and events such as hard braking, swerving, deceleration, are tracked and correlated to geographic locations. Event data for these incidents may be collected, aggregated, anonymized, and electronically communicated to a processing system for further analysis and identification of problematic roadway and traffic conditions.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventor: Matthew R. Torgerson
  • Methods, systems, and apparatus for progressive corrosion detection
    Patent number: 11175215
    Abstract: Apparatus, systems, and methods for progressive corrosion detection are disclosed. An example apparatus includes a query generator to query a multiplexer channel to receive an output voltage, the multiplexer channel linked to a fin group of an electrode array, the fin group forming an open circuit in the absence of conductive crystal formation, a quantifier to determine, using a reference voltage, a difference between the reference voltage and the output voltage from the queried multiplexer channel, and a contamination level comparator to identify presence of conductive crystal formation based on the difference between the reference voltage and the output voltage.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: November 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Thomas Birch, Barry Kennedy
  • Laser failure early warning indicator
    Patent number: 11177620
    Abstract: In embodiments, an apparatus to predict failure of a laser is presented. The apparatus may include a memory to store a reference model of bias current change for a laser as a function of time and temperature, one or more sensors to detect: temperature, elapsed operating time and bias current of the laser, and a processor communicatively coupled to the memory and to the one or more sensors. The processor may be to calculate an actual bias current change ?IA at a current laser temperature, and an expected bias current change ?IE, based at least in part on the reference model and an average operating temperature, subtract ?IE from ?IA, and if the difference is greater than a pre-defined value ?, output a signal. Related methods and non-transitory computer-readable media may also be presented.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Mahan Movassaghi, Rohit Mittal, Robert W. Herrick, Jen-Chyun Chen
  • Data plane interface network quality of service in multi-tenant data centers
    Patent number: 11178023
    Abstract: Methods, apparatus, and systems for data plane interface network Quality of Service (QoS) in multi-tenant data centers. Data plane operations including packet generation and encapsulation are performed in software running in virtual machines (VMs) or containers hosted by a compute platform. Control plane operations, including QoS traffic classification, are implemented in hardware by a network controller. Work submission and work completion queues are implemented in software for each VM or container. Work elements (WEs) defining work to be completed by the network controller are generated by software and processed by the network controller to classify packets associated with the WEs into QoS traffic classes, wherein packets belonging to a give traffic flow are classified to the same QoS traffic class.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Parthasarathy Sarangam, Anjali Jain, Kevin Scott
  • Adaptive resolution of point cloud and viewpoint prediction for video streaming in computing environments
    Patent number: 11178373
    Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: November 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Mayuresh Varerkar, Stanley Baran, Michael Apodaca, Prasoonkumar Surti, Atsuo Kuwahara, Narayan Biswal, Jill Boyce, Yi-Jen Chiu, Gokcen Cilingir, Barnan Das, Atul Divekar, Srikanth Potluri, Nilesh Shah, Archie Sharma
  • Techniques for multi-read and multi-write of memory circuit
    Patent number: 11176994
    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Somnath Paul, Charles Augustine, Turbo Majumder, Suyoung Bang
  • Techniques for dynamic multi-storage format database access
    Patent number: 11176091
    Abstract: Techniques and apparatus for providing access to data in a plurality of storage formats are described. In one embodiment, for example, an apparatus may include logic, at least a portion of comprised in hardware coupled to the at least one memory, to determine a first storage format of a database operation on a database having a second storage format, and perform a format conversion process responsive to the first storage format being different than the second storage format, the format conversion process to translate a virtual address of the database operation to a physical address, and determine a converted physical address comprising a memory address according to the first storage format. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Mark A. Schmisseur, Thomas Willhalm, Francesc Guim Bernat, Karthik Kumar
  • Skin map-aided skin smoothing of images using a bilateral filter
    Patent number: 11176641
    Abstract: Skin smoothing is applied to images using a bilateral filter and aided by a skin map. In one example a method includes receiving an image having pixels at an original resolution. The image is buffered. The image is downscaled from the original resolution to a lower resolution. A bilateral filter is applied to pixels of the downscaled image. The filtered pixels of the downscaled image are blended with pixels of the image having the original resolution, and the blended image is produced.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: November 16, 2021
    Assignee: INTEL CORPORATION
    Inventors: Liu Yang, Weike Chen, Lin Xu
  • INTEGRATED CIRCUIT STRUCTURES IN PACKAGE SUBSTRATES
    Publication number: 20210351116
    Abstract: Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.
    Type: Application
    Filed: July 19, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Sanka Ganesan, William James Lambert, Zhichao Zhang, Sri Chaitra Jyotsna Chavali, Stephen Andrew Smith, Michael James Hill, Zhenguo Jiang
  • THERMAL COOLING SYSTEM
    Publication number: 20210349509
    Abstract: Particular embodiments described herein provide for a device that can include at least one heat source and a vapor chamber, where the vapor chamber is bigger than the at least one heat source and a portion of the vapor chamber is in direct contact with the at least one heat source, where the portion of the vapor chamber in direct contact with the at least one heat source does not include a stiffener. In an example, the device can include a first air mover on a first side of the at least one heat source and a second air mover on an opposite side of the at least one heat source. Exhaust from the first air mover can pass through a vented foot and exhaust from the second air mover can pass through a second vented foot.
    Type: Application
    Filed: July 23, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: James Utz, Baomin Liu, Eduardo Escamilla
  • APPARATUS, SYSTEM AND METHOD OF TRANSMITTING A PPDU
    Publication number: 20210351859
    Abstract: An apparatus of a transmitter may include, for example, a Golay builder to build modulated Golay sequences for at least a non-EDMG Short Training Field (L-STF), and a non-EDMG Channel Estimation Field (L-CEF) of a PPDU; a scrambler to generate scrambled bits by scrambling bits of a non-EDMG header (L-header) and a data field of the PPDU; an encoder to encode the scrambled bits into encoded bits according to a low-density parity-check (LDDC) code; a constellation mapper to map the encoded bits into a stream of constellation points according to a constellation scheme; a spreader to spread the stream of constellation points according to a Golay sequence; and a transmit chain mapper to map a bit stream output from the Golay builder and the spreader to a plurality of transmit chains by applying a spatial expansion with relative cyclic shift over the plurality of transmit chains.
    Type: Application
    Filed: June 14, 2021
    Publication date: November 11, 2021
    Applicant: INTEL IP CORPORATION
    Inventors: Alexander Maltsev, Carlos Cordeiro, Artyom Lomayev, Michael Genossar, Claudio Da Silva
  • COMPACTION OF DIVERGED LANES FOR EFFICIENT USE OF ALUS
    Publication number: 20210349717
    Abstract: Described herein is an accelerator device in which compaction of diverged lanes of a parallel processor is enabled to increase the efficiency of ALU utilization. One embodiment provides an accelerator device comprising a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including a parallel processing architecture configured to enable compaction of diverged lanes.
    Type: Application
    Filed: June 26, 2020
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Chandra Gurram, Subramaniam Maiyuran, Supratim Pal, Saurabh Sharma, Aditya Navale
  • HIERARCHICAL GENERAL REGISTER FILE (GRF) FOR EXECUTION BLOCK
    Publication number: 20210349715
    Abstract: In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: May 12, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Abhishek R. Appu, Altug Koker, Joydeep Ray, Kamal Sinha, Kiran C. Veernapu, Subramaniam Maiyuran, Prasoonkumar Surti, Guei-Yuan Lueh, David Puffer, Supratim Pal, Eric J. Hoekstra, Travis T. Schluessler, Linda L. Hurd
  • TECHNIQUES TO DETECT FUSIBLE OPERATORS WITH MACHINE LEARNING
    Publication number: 20210350234
    Abstract: Various embodiments are generally directed to techniques to detect fusible operators with machine learning, such as by evaluating a set of operators in a graph of a machine learning model to identify fusion candidates comprising subgraphs of the graph with two or more operators to combine, for instance. Some embodiments are particularly directed to utilizing a machine learning classifier to evaluate fusion candidates using a set of features of the fusion candidate.
    Type: Application
    Filed: January 28, 2019
    Publication date: November 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Weifeng YAO, Xiao HU, Hongpeng MA, Yanan LIU, Huan H. ZHOU, Xiaokun YU, Zijie LU
  • ABSTRACTION LIBRARY TO ENABLE SCALABLE DISTRIBUTED MACHINE LEARNING
    Publication number: 20210350212
    Abstract: One embodiment provides for a non-transitory machine readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations comprising providing an interface to define a neural network using machine-learning domain specific terminology, wherein the interface enables selection of a neural network topology and abstracts low-level communication details of distributed training of the neural network.
    Type: Application
    Filed: May 24, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: DHIRAJ D. KALAMKAR, KARTHIKEYAN VAIDYANATHAN, SRINIVAS SRIDHARAN, DIPANKAR DAS
  • COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS
    Publication number: 20210350499
    Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of processing cores of a first type and a second type. A first set of processing cores of a first type perform multi-dimensional matrix operations and a second set of processing cores of a second type perform general purpose graphics processing unit (GPGPU) operations.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh, Nicolas C. Galoppo Von Borries, Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Sara S. Baghsorkhi, Justin E. Gottschlich, Altug Koker, Nadathur Rajagopalan Satish, Farshad Akhbari, Dukhwan Kim, Wenyin Fu, Travis T. Schluessler, Josh B. Mastronarde, Linda L. Hurd, John H. Feit, Jeffery S. Boles, Adam T. Lake, Karthik Vaidyanathan, Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu
  • PREDICTIVE VIEWPORT RENDERER AND FOVEATED COLOR COMPRESSOR
    Publication number: 20210350597
    Abstract: An embodiment of a graphics apparatus may include a focus identifier to identify a focus area, and a color compressor to selectively compress color data based on the identified focus area. Another embodiment of a graphics apparatus may include a motion detector to detect motion of a real object, a motion predictor to predict a motion of the real object, and an object placer to place a virtual object relative to the real object based on the predicted motion of the real object. Another embodiment of a graphics apparatus may include a frame divider to divide a frame into viewports, a viewport prioritizer to prioritize the viewports, a renderer to render a viewport of the frame in order in accordance with the viewport priorities, and a viewport transmitter to transmit a completed rendered viewport. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: March 8, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Deepak S. Vembar, Atsuo Kuwahara, Chandrasekaran Sakthivel, Radhakrishnan Venkataraman, Brent E. Insko, Anupreet S. Kalra, Hugues Labbe, Abhishek R. Appu, Ankur N. Shah, Joydeep Ray, ElMoustapha Ould-Ahmed-Vall, James M. Holland
  • METHOD AND APPARATUS FOR ACCURATE MEASUREMENT OF PLATFORM POWER
    Publication number: 20210349134
    Abstract: A Power Management Controller (PMC) which manages power states of a platform, informs a power accumulator device to start measuring the platform power during entry into the low power state (e.g., S0iX). The power accumulator device starts measuring the power until a stop message comes from the PMC. The PMC on detection of any wake event initiates a stop message to the power accumulator device. Once an operating system (OS) context is restored, software can read the measured data from the power accumulator device. The measured data is accessible to a host software using standard software application programming interface (API) and can be used to influence the power policies of the system.
    Type: Application
    Filed: December 1, 2020
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Sriram Ranganathan, Naveen G, Pannerkumar Rajagopal, Govindaraj Gettimalli, Javahar Ragothaman
  • TRAINING WITH ADAPTIVE RUNTIME AND PRECISION PROFILING
    Publication number: 20210350215
    Abstract: A mechanism is described for facilitating efficient training of neural networks at computing devices. A method of embodiments, as described herein, includes detecting one or more inputs for training of a neural network, and introducing randomness in floating point (FP) numbers to prevent overtraining of the neural network, where introducing randomness includes replacing less-significant low-order bits of operand and result values with new low-order bits during the training of the neural network.
    Type: Application
    Filed: May 18, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Brian T. Lewis, Rajkishore Barik, Murali Sundaresan, Leonard Truong, Feng Chen, Xiaoming Chen, Mike B. MacPherson
  • MIMO AND BANDWIDTH SIGNALING IN MILLIMETER-WAVE SYSTEMS
    Publication number: 20210351817
    Abstract: Techniques to enable dynamic bandwidth management at the physical layer level while maintaining backwards compatibility in wireless systems is provided. Furthermore, techniques for reducing the occurrence of exposed nodes are provided. A transmitter may transmit a frame including an indication that a PHY layer sub-header defining a bandwidth associated with a channel is present. Furthermore, the transmitter may transmit a third frame after receiving a second frame from a receiver to indicate to legacy stations that the TXOP was successful.
    Type: Application
    Filed: March 24, 2021
    Publication date: November 11, 2021
    Applicant: Intel IP Corporation
    Inventors: Carlos Cordeiro, Assaf Kasher, Solomon Trainin
  • REMOTE MANAGEMENT FOR A COMPUTING DEVICE
    Publication number: 20210352148
    Abstract: Examples are disclosed for remote management of a computing device. In some examples, a secure communication link may be established between a network input/output device for a computing device and a remote management application. Commands may be received from the remote management application and management functions may be implemented at the network input/output device. Implementation of the management functions may enable the remote management application to manage or control at least some operating parameters of the computing device. Other examples are described and claimed.
    Type: Application
    Filed: December 7, 2020
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventor: Patrick G. Kutch
  • FINE FEATURE FORMATION TECHNIQUES FOR PRINTED CIRCUIT BOARDS
    Publication number: 20210352807
    Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Eric Li, Kemal Aygun, Kai Xiao, Gong Ouyang, Zhichao Zhang
  • CLASS OF SERVICE
    Publication number: 20210349831
    Abstract: Described herein is an accelerator device having a cache memory for which limits may be specified for a memory allocation according to a class of service associated with a thread, application, or virtual machine that created the memory allocation. The limits can include a specific set of enumerated cache ways that are designated as eligible to cache data for memory allocations associated with a class of service.
    Type: Application
    Filed: June 25, 2020
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: NIRANJAN L. COORAY, ARAVINDH ANANTARAMAN, K. PATTABHIRAMAN, ANKUR SHAH
  • LOW RANK MATRIX COMPRESSION
    Publication number: 20210350585
    Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 10, 2021
    Publication date: November 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Tomer Bar-On, Jacob Subag, Yaniv Fais, Jeremie Dreyfuss, Gal Novik, Gal Leibovich, Tomer Schwartz, Ehud Cohen, Lev Faivishevsky, Uzi Sarel, Amitai Armon, Yahav Shadmiy
  • TECHNIQUES FOR PREVENTING MEMORY TIMING ATTACKS
    Publication number: 20210351911
    Abstract: Techniques and apparatuses for detecting and preventing memory attacks are described. In one embodiment, for example, an apparatus may include at least one memory comprising a shared memory and a system memory, logic, at least a portion of the logic comprised in hardware coupled to the at least one shared memory, the logic to implement a memory monitor to determine a memory attack by an attacker application against a victim application using the shared memory, and prevent the memory attack, the memory monitor to determine that victim data is being reloaded into the shared memory from the system memory, store the victim data in a monitor memory, flush shared memory data stored in the shared memory, and write the victim data to the shared memory. Other embodiments are described and claimed.
    Type: Application
    Filed: July 23, 2021
    Publication date: November 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Nagaraju N. Kodalapura, Arun Kanuparthi
  • METHOD AND APPARATUS FOR KEEPING STATISTICAL INFERENCE ACCURACY WITH 8-BIT WINOGRAD CONVOLUTION
    Publication number: 20210350210
    Abstract: A method and apparatus for keeping statistical inference accuracy with 8-bit winograd convolution. A calibration dataset and a pretrained CNN comprising 32-bit floating point weight values may be sampled to generate an input activation tensor and a weight tensor. A transformed input activation tensor may be generated by multiplying the input activation tensor and an input matrix to generate a transformed input activation tensor. A transformed weight tensor may be generated by multiplying the weight tensor and a weight matrix. A scale factor may be computed for each transformed tensor. An 8-bit CNN model including the scale factors may be generated.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Jiong GONG, Haihao SHEN, Xiao Dong LIN, Xiaoli LIU
  • INTELLIGENT PREDICTION OF PROCESSOR IDLE TIME APPARATUS AND METHOD
    Publication number: 20210349519
    Abstract: A machine-learning (ML) scheme running a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on time of day, and/or system telemetry. The ML creates a High Water Mark (HWM) number of dirty cache lines (DL) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DL to inform the low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Leo Aqrabawi, Chia-hung S. Kuo, James G. Hermerding II, Premanand Sakarda, Bijan Arbab, Kelan Silvester
  • SYSTEM CACHE OPTIMIZATIONS FOR DEEP LEARNING COMPUTE ENGINES
    Publication number: 20210349835
    Abstract: In an example, an apparatus comprises a plurality of compute engines; and logic, at least partially including hardware logic, to detect a cache line conflict in a last-level cache (LLC) communicatively coupled to the plurality of compute engines; and implement context-based eviction policy to determine a cache way in the cache to evict in order to resolve the cache line conflict. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: May 4, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Neta Zmora, Eran Ben-Avi
  • Power Management for Wireless Networks
    Publication number: 20210352584
    Abstract: Embodiments provide techniques for device power management in wireless networks. For instance, an apparatus may include a power management module, and a transceiver module. The power management module determines a beacon interval and a wakeup interval. The transceiver module to send a transmission to one or more remote devices that includes the beacon interval and the wakeup interval. The beacon interval indicates a time interval between consecutive beacon transmissions of the apparatus, and the wakeup interval indicates a time interval between when the apparatus receives two consecutive beacons from a peer device.
    Type: Application
    Filed: March 24, 2021
    Publication date: November 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Xiaohong Gong, Jesse Walker
  • VERTICALLY STACKED TRANSISTORS IN A FIN
    Publication number: 20210351078
    Abstract: An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Aaron D. Lilak, Sean T. Ma, Justin R. Weber, Patrick Morrow, Rishabh Mehandru
  • SCALAR CORE INTEGRATION
    Publication number: 20210349848
    Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: May 17, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: JOYDEEP RAY, ARAVINDH ANANTARAMAN, ABHISHEK R. APPU, ALTUG KOKER, ELMOUSTAPHA OULD-AHMED-VALL, VALENTIN ANDREI, SUBRAMANIAM MAIYURAN, NICOLAS GALOPPO VON BORRIES, VARGHESE GEORGE, MIKE MACPHERSON, BEN ASHBAUGH, MURALI RAMADOSS, VIKRANTH VEMULAPALLI, WILLIAM SADLER, JONATHAN PEARCE, SUNGYE KIM
  • SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS WITH FEEDBACK INPUTS
    Publication number: 20210349966
    Abstract: Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic array with feedback inputs.
    Type: Application
    Filed: June 26, 2020
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: SUBRAMANIAM MAIYURAN, JORGE PARRA, SUPRATIM PAL, ASHUTOSH GARG, SHUBRA MARWAHA, CHANDRA GURRAM, DARIN STARKEY, DURGESH BORKAR, VARGHESE GEORGE
  • DIFFERENTIAL ON-CHIP LOOP ANTENNA
    Publication number: 20210351511
    Abstract: Aspects of the embodiments are directed to an on-chip loop antenna and methods of manufacturing the same. In some embodiments, the on-chip loop antenna is in an integrated circuit (IC) die. The IC die comprises metal loops substantially centered around a core region of the IC die in a metallization stack of the IC die, a dielectric between spaces of the metal loops, an electric circuit in the core region electrically connected to the metal loops with an interconnect, and a ground plane in the metallization stack electrically connected to the loops with a first plurality of vias and to the electric circuit with a second plurality of vias. The first plurality of vias is different from the second plurality of vias, and the electric circuit includes an inductor. In some embodiments, the on-chip loop antenna can be carried by a semiconductor package.
    Type: Application
    Filed: July 20, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Nir Weisman, Omer Asaf, Eyal Goldberger
  • WAVE SPRING-BASED INTERCONNECT PROBES
    Publication number: 20210351535
    Abstract: In one embodiment, an interconnect apparatus (e.g., an interposer apparatus) includes a plurality of interconnect probes that each include a wave spring structure that includes a plurality of stacked wave spring discs. The wave spring discs may be formed in a sinusoidal wave form shape, or in another wave form shape.
    Type: Application
    Filed: July 23, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Ismael Franco Núñez, Daqiao Du, Zhen Zhou, Gordon P. Melz
  • ACCURATE LOAD CURRENT SENSING APPARATUS AND METHOD
    Publication number: 20210351697
    Abstract: A Ton/2 generator retrofits a digital tracking algorithm to an analog Constant-On-Time (COT) Controller to enable fast sensing. The Ton/2 generation is cognizant of the delay between high-side switch (HSFET) on generation and the actual turn-on time of the HSFET so that there is no deviation of sampling point, and current is reported with high accuracy. The digital tracking algorithm automatically takes higher steps during load transients to enable faster tracking and scales the measured current (Ipeak/2) based on a discontinuous conduction mode (DCM) period for DCM current reporting.
    Type: Application
    Filed: December 2, 2020
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Shobhit Tyagi, Saurabh Verma
  • DEFENSE AGAINST SPECULATIVE SIDE-CHANNEL ANALYSIS OF A COMPUTER SYSTEM
    Publication number: 20210349634
    Abstract: Embodiments of methods and apparatuses for defending against speculative side-channel analysis on a computer system are disclosed. In an embodiment, a processor includes a decoder, a cache, address translation circuitry, a cache controller, and a memory controller. The decoder is to decode an instruction. The instruction is to specify a first address associated with a data object, the first address having a first memory tag. The address translation circuitry is to translate the first address to a second address, the second address to identify a memory location of the data object. The comparator is to compare the first memory tag and a second memory tag associated with the second address. The cache controller is to detect a cache miss associated with the memory location.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventor: David M. Durham
  • LOW POWER APPARATUS AND METHOD TO MULTIPLY FREQUENCY OF A CLOCK
    Publication number: 20210351779
    Abstract: A multi-feedback circuit that compares a duty cycle corrected reference clock fREF, and controls a number of identical delay lines to generate a new clock with a frequency that is a multiple (e.g., 32×, 4×, etc.) of the frequency of fREF with approximately 50% duty cycle (DC). The new clock is used as a reference clock to a phase locked loop (PLL) or a multiplying delay locked loop (MDLL) resulting in shorter lock times for the PLL/MDLL, higher bandwidth for the PLL/MDLL, lower long-term output clock jitter. The multi-feedback circuit can also be used as a low power clock generator.
    Type: Application
    Filed: May 8, 2020
    Publication date: November 11, 2021
    Applicant: Intel Corporation
    Inventors: Kuan-Yueh Shen, Nasser Kurd
  • Method for intelligent roaming in a client station over single or multiple WLANs
    Patent number: 11172439
    Abstract: An method for a wireless station to select an access point among a plurality of access point possibilities using a combination of characteristics about each access point such as signal strength, access point load, protocol, maximum throughput, multi-user MIMO capability, and channel load.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: November 9, 2021
    Assignee: INTEL CORPORATION
    Inventors: Wayne Grosvenor Dunlap, James Ho Wang