Abstract: Embodiments disclosed herein include electronic packages and thermal solutions for such electronic packages. In an embodiment, an electronic package comprises, a package substrate with a first surface, a second surface opposite from the first surface, and a sidewall surface connecting the first surface to the second surface. In an embodiment, the electronic package further comprises a heat spreader, where a first portion of the heat spreader is attached to the first surface of the package substrate and a second portion of the heat spreader is attached to the second surface of the package substrate. In an embodiment, a third portion of the heat spreader adjacent to the sidewall surface of the package substrate connects the first portion of the heat spreader to the second portion of the heat spreader.

Abstract: Methods, apparatuses, and computer readable media for communicating elements between multi-link devices are disclosed. Apparatuses of a first access points (AP) of an AP multi-link device (MLD) are disclosed, where the apparatuses comprise processing circuitry configured to encode a first portion of a first beacon frame or first response frame, and in response to a second AP of the AP MLD transmitting, on a second frequency band, a second beacon frame or a second probe response frame comprising a channel switch announcement element or an enhanced channel switch announcement frame, encoding a second portion of the first beacon frame or the first probe response frame, the second portion comprising the channel switch announcement element or the enhanced channel switch announcement frame. The processing circuitry is further configured to configure the first AP of the AP MLD to transmit, on a first frequency band, the first beacon frame.

Abstract: Apparatuses, methods, and articles of manufacture are disclosed. An example apparatus includes processor circuitry to assign a location value hyperdimensional vector (HDV) to a location in an image of a first patch of one or more pixels, assign at least a first channel HDV to the first patch, determine at least one pixel intensity value HDV for each of the one or more pixels in the first patch, bind together each of the pixel intensity value HDVs into at least one patch intensity value HDV, bind together the at least first channel HDV and the at least one patch intensity value HDV to produce a patch consensus intensity HDV, and generate a first hyperdimensional representation patch value HDV of the first patch by binding together at least a combination of the patch consensus intensity HDV and the location value HDV.

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatuses, techniques, and/or processes directed to packages that include stacked dies that use thermal conductivity features including thermally conductive through silicon vias (TSVs) filled with thermally conductive material located in passive areas of a first die to route heat from a first die away from a second die that is coupled with the first die. In embodiments, the first die may be referred to as a base die. Embodiments may include thermal blocks in the form of dummy dies that include TSVs at least partially filled with thermal energy conducting material such as copper, solder, or other alloy.

Abstract: An example electronic apparatus is for accelerating a para-virtualization network interface. The electronic apparatus includes a descriptor hub performing bi-directionally communication with a guest memory accessible by a guest and with a host memory accessible by a host. The guest includes a plurality of virtual machines. The host includes a plurality of virtual function devices. The virtual machines are communicatively coupled to the electronic apparatus through a central processing unit. The communication is based upon para-virtualization packet descriptors and network interface controller virtual function-specific descriptors. The electronic apparatus also includes a device association table communicatively coupled to the descriptor hub and to store associations between the virtual machines and the virtual function devices. The electronic apparatus further includes an input-output memory map unit (IOMMU) to perform direct memory access (DMA) remapping and interrupt remapping.

Abstract: Systems, apparatuses and methods may provide for technology that dynamically tunes platform features based on virtual machine runtime requirements. In one example, a first virtual machine and a second virtual machine of a cloud server platform may each be associated with one or more logical cores. The first virtual machine may have a first configuration to efficiently support a first feature setting arrangement on the associated logical cores. The second virtual machine may have a different second configuration to efficiently support a different second feature setting arrangement on the different associated logical cores. Feature settings that are specific to an application associated with a virtual machine may be determined based on application runtime requirements. Such determined feature settings may be stored as a bit mask in control fields of a virtual machine control and enforced on the logical cores associated with a given virtual machine.

Abstract: Technologies for providing policy-based secure containers for multiple enterprise applications include a client computing device and an enterprise policy server. The client computing device sends device attribute information and a request for access to an enterprise application to the enterprise policy server. The enterprise policy server determines a device trust level based on the device attribute information and a data sensitivity level based on the enterprise application, and sends a security policy to the client computing device based on the device trust level and the data sensitivity level. The client computing device references or creates a secure container for the security policy, adds the enterprise application to the secure container, and enforces the security policy while executing the enterprise application in the secure container. Multiple enterprise applications may be added to each secure container. Other embodiments are described and claimed.

Abstract: Lost, misplaced, incorrectly delivered, and damaged assets are a common occurrence in shipment or asset tracking. Disclosed are various embodiments concerning a battery-less or intermittent battery use environments in which a node uses internal logic (e.g., circuitry and/or software) that, based at least in part on sensor information and stored information regarding the history of the node, may track events that have occurred to the node. The node may be responsive to events and determine whether exceptions have occurred that require attention. For example, detecting damage might cause the node to update an output to indicate the node and associated material, if any, needs to be rerouted to address the exception.

Abstract: Techniques for decoupled access-execute near-memory processing include examples of first or second circuitry of a near-memory processor receiving instructions that cause the first circuitry to implement system memory access operations to access one or more data chunks and the second circuitry to implement compute operations using the one or more data chunks.

Abstract: The techniques described herein relate to a Radio Frequency (RF) communication module for a hand-held mobile electronic device. The Radio Frequency (RF) communication module includes a circuit board and a plurality of antennas disposed on a top side and bottom side of the circuit board. The plurality of antennas comprise a first subset of antennas comprising end-fire antennas and a second subset of antennas comprising broadside antennas. The first subset of antennas and the second subset of antennas also have a bandwidth of approximately 40 percent. The Radio Frequency (RF) communication module also includes a shielded area comprising circuitry coupled to the circuit board for controlling the antennas.

Abstract: A memory circuit includes first and second inverters that are cross coupled. The first inverter is configured to provide a first drive current from a first supply line to store a first logic state in the memory circuit. The first drive current is larger than a second drive current that the second inverter is configured to provide from the first supply line to store a second logic state in the memory circuit.

Abstract: One embodiment provides for a machine-learning accelerator device a multiprocessor to execute parallel threads of an instruction stream, the multiprocessor including a compute unit, the compute unit including a set of functional units, each functional unit to execute at least one of the parallel threads of the instruction stream. The compute unit includes compute logic configured to execute a single instruction to scale an input tensor associated with a layer of a neural network according to a scale factor, the input tensor stored in a floating-point data type, the compute logic to scale the input tensor to enable a data distribution of data of the input tensor to be represented by a 16-bit floating point data type.

Abstract: Omni-scale convolution for convolutional neural networks is disclosed. An example of an apparatus includes one or more processors to process data, including processing for a convolutional neural network (CNN); and a memory to store data, including CNN data, wherein processing of input data by the CNN includes implementing omni-scale convolution in one or more convolutional layers of the CNN, implementation of the omni-scale convolution into a convolutional layer of the one or more convolutional layers including at least applying multiple dilation rates in a plurality of kernels of a kernel lattice of the convolutional layer, and applying a cyclic pattern for the multiple dilation rates in the plurality of kernels of the convolutional layer.

Abstract: Performing online learning for a model to detect unseen actions in an action recognition system is disclosed. The method includes extracting semantic features in a semantic domain from semantic action labels, transforming the semantic features from the semantic domain into mixed features in a mixed domain, and storing the mixed features in a feature database. The method further includes extracting visual features in a visual domain from a video stream and determining if the visual features indicate an unseen action in the video stream. If no unseen action is determined, applying an offline classification model to the visual features to identify seen actions, assigning identifiers to the identified seen actions, transforming the visual features from the visual domain into mixed features in the mixed domain, and storing the mixed features and seen action identifiers in the feature database.

Abstract: Techniques and mechanisms for processor circuitry to execute a load and expand instruction of an instruction set to generate decompressed matrix data. In an embodiment, the instruction comprises a source operand which indicates a location from which compressed matrix data, and corresponding metadata, are to be accessed. A destination operand of the instruction indicates a location which is to receive decompressed metadata, which is generated, during execution of the instruction, based on the compressed matrix data and the corresponding metadata. The metadata comprises compression mask information which identifies which elements of the matrix have been masked from the compressed matrix data. In another embodiment, the instruction further comprises a count operand which identifies a total number of the unmasked matrix elements which are represented in the compressed matrix data.

Abstract: Technologies for protocol execution include a command device to broadcast a protocol message to a plurality of computing devices and receive an aggregated status message from an aggregation system. The aggregated status message identifies a success or failure of execution of instructions corresponding with the protocol message by the plurality of computing devices such that each computing device of the plurality of computing devices that failed is uniquely identified and the success of remaining computing devices is aggregated into a single success identifier.

Abstract: Techniques related to adaptive quantization matrix selection using machine learning for video coding are discussed. Such techniques include applying a machine learning model to generate an estimated quantization parameter for a frame and selecting a set of quantization matrices for encode of the frame from a number of sets of quantization matrices based on the estimated quantization parameter.

Abstract: For example, an Access Point (AP) may be configured to determine that a high-priority contention period is to be initiated during a particular contention period. For example, the AP may be configured to determine that the high-priority contention period is to be initiated during the particular contention period based on a reservation signal received from a station (STA) over a wireless medium during the particular contention period. For example, the AP may be configured to allow the AP to contend the wireless medium during the high-priority contention period according to a high-priority contention policy, for example, to obtain a Transmit Opportunity (TxOP) for transmission of downlink (DL) data to one or more STAs.

Abstract: In one embodiment, an integrated circuit package includes a package substrate with a cavity, an integrated circuit device, a bridge, a photonic integrated circuit (PIC), and an electronic integrated circuit (EIC). The integrated circuit device is electrically coupled to the package substrate. The bridge and the PIC are in the cavity of the package substrate, and the bridge is electrically coupled to the package substrate. The EIC is above, and electrically coupled to, the bridge and the PIC.

Abstract: An apparatus is provided which comprises: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, and a second layer formed on the second surface of the first die; a second die coupled to the first layer; and a plurality of structures to couple the apparatus to an external component, wherein the plurality of structures is coupled to the second layer.

Abstract: Techniques for selective disable of history-based predictors on mode transitions are described. An example apparatus comprises first circuitry to provide a history-based prediction, and second circuitry coupled to the first circuitry to selectively block and unblock a prediction from the first circuitry after a mode transition. Other examples are disclosed and claimed.

Abstract: Techniques for interface conversion and unicast for test content, firmware, and software delivery are described. An example apparatus comprises a scan test interface coupled to multiple circuits blocks to perform a scan test for the multiple circuit blocks, and circuitry coupled to input/output (IO) signals of the scan test interface to provide content for the multiple circuit blocks and to deliver a replicated content to multiple endpoints of the multiple circuit blocks (e.g., unicast technology). In another example, the circuitry is coupled to the IO signals of the scan test interface and a system/communication interface to decode packets received at the IO signals and convert the decoded packets to provide content through the system/communication interface for the multiple circuit blocks. Other examples are described and claimed.

Abstract: Logic to determine a first set of packets for transmission to a second STA in an aggregated medium access control (MAC) protocol data unit (A-MPDU). Logic to identify a retransmission scheme to determine a first number of packets to transmit based on the first set of packets. Logic to generate network coded packets for transmission in the A-MPDU, wherein the network coded packets comprise encoded combinations of the first set of packets. Logic to generate the A-MPDU for transmission to the second STA with the first number of packets. Logic to cause transmission of the A-MPDU. And logic to receive a block acknowledgement (BlockAck) comprising a feedback value, wherein the feedback value is a number of additional network coded packets requested by the second STA to decode the first set of packets or a number of packets received by the second STA.

Abstract: An embodiment of an integrated circuit may comprise memory to store respective resource control descriptors in correspondence with respective identifiers, and an input/output (JO) memory management unit (IOMMU) communicatively coupled to the memory, the IOMMU including circuitry to determine resource control information for an IO transaction based on a resource control descriptor stored in the memory that corresponds to an identifier associated with the IO transaction, and control utilization of one or more resources of the IOMMU based on the determined resource control information. Other embodiments are disclosed and claimed.

Abstract: Embodiments of a microelectronic assembly comprise a first integrated circuit (IC) die having first bond-pads on a first surface; an organic dielectric material in contact with the first surface; second bond-pads on a second surface of the organic dielectric material opposite to the first surface; through-dielectric vias (TDVs) in the dielectric material between the first bond-pads and the second bond-pads, wherein the TDVs are in direct contact with the first bond-pads and the second bond-pads; a second IC die embedded in the organic dielectric material and coupled to the first bond-pads by first interconnects; and a package substrate coupled to the second bond-pads by second interconnects.

Abstract: Optical connectivity for interconnects are described. A method includes determining an optical interconnect supports a defined optical mode, decoding electrical signals from an electrical interconnect, the electrical signals to represent a number of bits from one or more messages, converting the electrical signals to optical signals for the optical interconnect, and mapping the decoded bits to one or more optical channels of the optical interconnect. Other embodiments are described and claimed.

Abstract: An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.

Abstract: A computing device includes a flexible display screen, a housing to house at least one processor device and at least one memory element, and a first wing to support a side portion of the display screen. The front face of the housing includes a center portion of the display screen. The first wing is connected to the housing by a hinge, the first wing configured to swivel about an axis defined by the hinge. The hinge is configured to lock the first wing in at least two wing positions, a first of the wing positions supports the side portion of the display screen in a first orientation, a second of the wing positions supports the side portion of the display screen in a second orientation, and the side portion of the display screen is active in the first orientation and hidden in the second orientation.

Abstract: An apparatus to facilitate provenance audit trails for microservices architectures is disclosed. The apparatus includes one or more processors to obtain provenance metadata for a microservice from a local blockchain of provenance metadata maintained for the hardware resource executing a task performed by the microservice, the provenance metadata comprising identification of the microservice, operating state of at least one of a hardware resource or a software resource used to execute the microservice and the task, and an operating state of a sidecar of the microservice during the task; access one or more policies established for the microservice; analyze the provenance metadata with respect to the one or more policies to identify if there is a violation of the one or more policies; and generate one or more evaluation metrics based on whether the violation of the one or more policies is identified.

Abstract: In one embodiment, a transistor device includes a metal layer, a first dielectric layer comprising Hafnium and Oxygen on the metal layer, a channel layer comprising Tungsten and Selenium above the dielectric layer, a second dielectric layer comprising Hafnium and Oxygen on the channel layer, a source region comprising metal on a first end of the channel layer, a drain region comprising metal on a second end of the channel layer opposite the first end, and a metal contact on the second dielectric layer between the source regions and the drain region. In some embodiments, the transistor device may be included in a complementary metal-oxide semiconductor (CMOS) logic circuit in the back-end of an integrated circuit device, such as a processor or system-on-chip (SoC).

Abstract: Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.

Abstract: An apparatus is provided which comprises: one or more dielectric layers forming a substrate, one or more first conductive contacts on a top surface of the substrate, one or more second conductive contacts on a bottom surface of the substrate opposite of the top surface, and one or more discrete capacitors conductively coupled with one or more of the first and second conductive contacts, the one or more discrete capacitors embedded within the substrate between the top surface and the bottom surface. Other embodiments are also disclosed and claimed.

Abstract: A processor includes a range register to store information that identifies a reserved range of memory associated with a secure arbitration mode (SEAM) and a core coupled to the range register. The core includes security logic to unlock the range register on a logical processor, of the processor core, that is to initiate the SEAM. The logical processor is to, via execution of the security logic, store, in the reserved range, a SEAM module and a manifest associated with the SEAM module, wherein the SEAM module supports execution of one or more trust domains; initialize a SEAM virtual machine control structure (VMCS) within the reserved range of the memory that is to control state transitions between a virtual machine monitor (VMM) and the SEAM module; and authenticate the SEAM module using a manifest signature of the manifest.

Abstract: Techniques and mechanisms for determining a relative order in which respective microoperations of execution threads are performed. In an embodiment, a processor comprises a control register and circuitry which enables an executing program to set a control parameter which is provided by the control register. The control parameter determines whether the processor is to provide a control which applies one or more synchronization requirements to threads of execution which are of the same thread group. In another embodiment, the control is configurable to selectively provide implicit synchronization between some or all such threads.

Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.

Abstract: IC devices implementing 2T memory cells with angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. 2T memory cells with read and write transistors provided in different planes of an IC device, stacked substantially over one another, and having either the read transistors or the write transistors being angled transistors provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

Abstract: Valleytronic devices comprise a channel layer having ferrovalley properties—band-spin splitting and Berry curvature dependence on the polarization of the channel layer. Certain monochalcogenides possess these ferrovalley properties. Valleytronic devices utilize ferrovalley properties to store and/or carry information. Valleytronic devices can comprise a cross geometry comprising a longitudinal portion and a transverse portion. A spin-polarized charge current injected into the longitudinal portion of the device is converted into a voltage output across the transverse portion via the inverse spin-valley Hall effect whereby charge carriers acquire an anomalous velocity in proportion to the Berry curvature and an applied in-plane electric field resulting from an applied input voltage. Due to the Berry curvature dependency on the material polarization, switching the polarity of the input voltage that switches the channel layer polarization also switches the polarity of the differential output voltage.

Abstract: Described herein are optimized packet headers for Ethernet IP networks and related methods and devices. An example packet header includes a field comprising a source identifier (SID), the SID comprising a shortened representation of a complete Internet Protocol (IP) address of a source network device, a field comprising a destination identifier (DID), the DID comprising a shortened representation of a complete IP address of a destination network device, and a field having a total number of bits that is less than 8 and comprising a shortened representation of a type of encapsulation protocol for the packet. The packet header excludes fields comprising the complete IP address and a media access controller (MAC) address of the source network device, fields comprising the complete IP address and the MAC address of the destination network device, a field comprising a header checksum, and a field comprising a total size of the packet.

Abstract: For example, a wireless communication Station (STA) may be configured to generate a preamble of a Physical Layer (PHY) Protocol Data Unit (PPDU) according to a PPDU frame format. For example the STA may be configured to generate a data payload of the PPDU according to the PPDU frame format. For example, the data payload may include a plurality of data payload portions. For example, the PPDU may include a predefined Training Field (TF) between a first data payload portion and a second data payload portion of the plurality of data payload portions. For example, the STA may be configured to transmit the PPDU.

Abstract: An apparatus to facilitate broadcast remote sealing for scalable trusted execution environment provisioning is disclosed. The apparatus includes a cloud service provider (CSP) execution platform comprising hardware circuitry for executing virtualized environments and comprising hardware accelerator devices, wherein the CSP execution platform to: authorize a tenant to deploy workloads of the tenant to CSP execution resources; provide a group status report to the tenant to inform the tenant of an existence and a status of a group of trusted execution platforms, wherein the group comprises at least one of the CSP execution resources; receive an encrypted workload of the tenant, wherein the encrypted workload is encrypted using a group public key of the group; store the encrypted workload at storage of the CSP execution platform; and dispatch the encrypted workload to the at least one of the CSP execution resources of the group.

Abstract: Machine learning models can generate outputs such as salient object detection. However, top-performing large-scale models have high computational cost, making the models hard to deploy on resource-constrained devices and to make predictions in real time. A difference convolution reparameterization technique can be used to fuse the sets of parameters learned during training time into a single set of parameters to be used at inference time or at deployment. The technique can increase performance without adding a lot of parameters. Furthermore, an efficient and effective spatial temporal difference convolution block can be used to leverage temporal information to make predictions. The spatial temporal difference convolution block can also apply the difference convolution reparameterization technique to reduce the need to increase parameters to achieve desired performance.

Abstract: IC devices implementing 2T memory cells with source-drain coupling in one transistor, and related assemblies and methods, are disclosed herein. In particular, 2T memory cells presented herein use first and second transistors arranged so that source and drain terminals of the second transistor are coupled to one another. A memory state may be represented by charge indicative of the bit value stored in the second transistor, while the first transistor may serve as a switch to control access to the second transistor. 2T memory cells with source-drain coupling in one transistor provide a promising way to increasing memory cell densities, drive current, and design flexibility in making electrical connections to, or between, various transistor terminals and control lines of memory arrays, thus providing good scalability in the number of 2T memory cells included in memory arrays.

Abstract: Methods and apparatus relating to cryptographic protection of memory attached over interconnects are described. In an embodiment, memory stores data and a processor having execution circuitry executes an instruction to program an inline memory expansion logic and a host memory encryption logic with one or more cryptographic keys. The inline memory expansion logic encrypts the data to be written to the memory and decrypts encrypted data to be read from the memory. The memory is coupled to the processor via an interconnect endpoint of a system fabric. Other embodiments are also disclosed and claimed.

Abstract: Microphones are located between pixel display elements (e.g., micro-LEDs and OLEDs) in a display. Display-integrated microphones allow displays to have thinner bezels. Audio processing components can also be incorporated into the display and allow audio processing offloading from processors external to the display. Arrays of microphones allow for the beamforming of received audio signals to enhance the detection of sound from remote audio sources. Piezoelectric elements can also be integrated into a display to allow for localized haptic feedback. Integrated piezoelectric elements can act as speakers and beamforming techniques can be used to activate sets of piezoelectric elements in coordination to direct sound to a specific location external to the display. Piezoelectric elements can aid in display thermal management by creating acoustic waves to move heated air within a display to create a more uniform thermal profile within the display or to remove excess heat from the display.

Abstract: This disclosure describes systems, methods, and devices related to power spectral density (PSD) limit. A device may generate a frame comprising one or more elements to be sent to a first station device, wherein the frame is to be sent using a 6 GHz band. The device may include in the frame, information associated with a PSD limit on a per bandwidth size basis of the 6 GHz band. The device may cause to send the frame to the first station device.

Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

Abstract: Technologies for untrusted code execution include a computing device having a processor with sandbox support. The computing device executes code included in a native domain in a non-privileged, native processor mode. The computing device may invoke a sandbox jump processor instruction during execution of the code in the native domain to enter a sandbox domain. The computing device executes code in the sandbox domain in a non-privileged, sandbox processor mode in response to invoking the sandbox jump instruction. While executing in the sandbox processor mode, the processor denies access to memory outside of the sandbox domain and may deny execution of one or more prohibited instructions. From the sandbox domain, the computing device may execute a sandbox exit instruction to exit the sandbox domain and resume execution in the native domain. The computing device may execute processor instructions to configure the sandbox domain. Other embodiments are described and claimed.

Abstract: A semiconductor device including a semiconductor chip having a first conduction element; a substrate having second and third conduction elements; and external connection elements configured to form an electrical path between the second and third conduction elements via the first conduction element.

Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.