Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

Abstract: Methods and systems are disclosed using an execution pipeline on a multi-processor platform for deep learning network execution. In one example, a network workload analyzer receives a workload, analyzes a computation distribution of the workload, and groups the network nodes into groups. A network executor assigns each group to a processing core of the multi-core platform so that the respective processing core handle computation tasks of the received workload for the respective group.

Abstract: Embodiments detailed herein relate to arithmetic operations of float-point values. An exemplary processor includes decoding circuitry to decode an instruction, where the instruction specifies locations of a plurality of operands, values of which being in a floating-point format. The exemplary processor further includes execution circuitry to execute the decoded instruction, where the execution includes to: convert the values for each operand, each value being converted into a plurality of lower precision values, where an exponent is to be stored for each operand; perform arithmetic operations among lower precision values converted from values for the plurality of the operands; and generate a floating-point value by converting a resulting value from the arithmetic operations into the floating-point format and store the floating-point value.

Abstract: Described are precursor compounds and methods for atomic layer deposition of films containing scandium(III) oxide or scandium(III) sulfide. Such films may be utilized as dielectric layers in semiconductor manufacturing processes, particular for depositing dielectric films and the use of such films in various electronic devices.

Abstract: An apparatus of a New Radio (NR) Node B (gNB), a method, and a storage medium. One or more processors of the apparatus are to: encode for transmission to a user equipment (UE) a message to configure the UE with a measurement gap pattern for positioning reference signal (PRS) measurements; and set a gap pattern length of a measurement gap corresponding to the measurement gap pattern depending on whether an overlap exists between a PRS to be measured and one or more other NR data scheduled to be received by the UE.

Abstract: A thermal interface structure may be formed comprising a thermally conductive substrate having a first surface and an opposing second surface, a first liquid metal layer on the first surface of the thermally conductive substrate, and a second liquid metal layer on the second surface of the thermally conductive substrate. The thermal interface structure may be used in an integrated circuit assembly or package between at least one integrated circuit device and a heat dissipation device.

Abstract: A clock generator calibration system can include a phased-locked loop and a correction circuit. The PLL can generate an output clock signal, and the correction circuit can adjust a frequency signal of the PLL based on a digital signal of the PLL. The digital signal can be generated based on the adjusted frequency signal.

Abstract: Systems, apparatuses and methods may provide for technology that determines a frame rate of video content, sets a blend amount parameter based on the frame rate, and temporally anti-aliases the video content based on the blend amount parameter. Additionally, the technology may detect a coarse pixel (CP) shading condition with respect to one or more frames in the video content and select, in response to the CP shading condition, a per frame jitter pattern that jitters across pixels, wherein the video content is temporally anti-aliased based on the per frame jitter pattern. The CP shading condition may also cause the technology to apply a gradient to a plurality of color planes on a per color plane basis and discard pixel level samples associated with a CP if all mip data corresponding to the CP is transparent or shadowed out.

Abstract: Examples herein relate to a solid state drive that includes a media, first circuitry, and second circuitry. In some examples, the first circuitry is to execute one or more commands. In some examples, the second circuitry is to receive a configuration of at one type of command, where the configuration is to define an amount of media bandwidth allocated for the at one type of command; receive a command; and assign the received command to the first circuitry for execution.

Abstract: In accordance with disclosed embodiments, there is an antenna package using a ball attach array to connect an antenna and base substrates of the package. One example is an RF module package including an RF antenna package having a stack material in between a top and a bottom antenna layer to form multiple antenna plane surfaces, a base package having alternating patterned conductive and dielectric layers to form routing through the base package, and a bond between a bottom surface of the antenna package and to a top surface of the base package.

Abstract: An apparatus to facilitate partially-frozen neural networks for efficient computer vision systems is disclosed. The apparatus includes a frozen core to store fixed weights of a machine learning model, one or more trainable cores coupled to the frozen core, the one or more trainable cores comprising multipliers for trainable weights of the machine learning model, and wherein the alpha blending layer includes a trainable alpha blending parameter, and wherein the trainable alpha blending parameter is a function of a trainable parameter, a sigmoid function, and outputs of frozen and trainable blocks in a preceding layer of the machine learning model.

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Abstract: Techniques related to calibrating fisheye cameras using a single image are discussed. Such techniques include applying a first pretrained convolutional neural network to an input fisheye image to generate camera model parameters excluding a principle point and applying a second pretrained convolutional neural network to the fisheye image and a difference of the fisheye image and a projection of the fisheye image using the camera model parameters to generate the principle point.

Abstract: Embodiments are directed to memory protection with hidden inline metadata to indicate data type and capabilities. An embodiment of a processor includes a processor core and cache memory. The processor core is to implant hidden inline metadata in one or more cachelines for the cache memory, the hidden inline metadata hidden at a linear address level, hidden from software, the hidden inline metadata to indicate data type or capabilities for the associated data stored on the same cacheline.

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

Abstract: Methods, apparatus, systems, and articles of manufacture to process high-speed video are disclosed. An example apparatus comprises at least one memory; instructions in the apparatus; and processor circuitry to execute the instructions to: interleave a plurality of images from a first camera and a second camera in chronological order, the first camera to capture first images of the plurality of images, the second camera to capture second images of the plurality of images at a different time offset than the first camera; and generate video with an adaptive frame rate from the plurality of images by applying a mask to the plurality of images.

Abstract: Technologies for providing hints for adjusting digital media properties include a destination computing device wirelessly coupled to multiple source computing devices. The destination computing device is configured to receive digital media streams from each of a multiple number of source computing devices, process each of the received digital media streams, and output one or more of the processed digital media streams based on one or more output settings and/or or more digital media properties of the digital media. The destination computing device is further configured to determine one or more performance metrics based on an analysis of the output digital media streams, determine one or more hints for one or more of the digital media streams based on the analysis, and transmit each of the hints to a corresponding one of the source computing devices. Other embodiments are described and claimed herein.

Abstract: Technologies for context-based management of wearable computing devices include a mobile computing device and a wearable computing device. The wearable computing device generates sensor data indicative of a location context of the wearable computing device and transmits the sensor data to the mobile computing device. The mobile computing device generates local sensor data indicative of a location context of the wearable computing device and fuses the local sensor data with the sensor data received from the wearable computing device. The mobile computing device determines a context of the wearable computing device based on the fused sensor data. The mobile computing device determines whether an adjustment to the functionality of the wearable computing device is required based on the determined context. The mobile computing device manages the functionality of the wearable computing device in response to determining that an adjustment to the functionality is required.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.

Abstract: Various embodiments herein are directed to multi-Transmission Time Interval (TTI) scheduling for data transmission for system operating above the 52.6 GHz carrier frequency. Other embodiments may be disclosed and/or claimed.

Abstract: A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.

Abstract: The present disclosure is directed to systems and methods for improving the rigidity or stiffness of an electronic device chassis or housing using a structural secondary battery. The structural secondary battery includes a compression skin disposed about one or more secondary storage cells. The compression skin exerts a compressive force of at least 0.5 atmospheres on the one or more secondary storage cells. A structural member is bonded to the compression skin. The structural member includes a relatively thin (e.g. 0.1 mm or less), rigid (e.g., Young's Modulus of at least 300 GPa), member, such as a sapphire crystal. The structural member may then be bonded or otherwise detachably or non-detachably affixed to an aperture formed in the electronic device chassis or housing. The bonding of the structural member to the electronic device chassis or housing beneficially improves the stiffness of the chassis or housing.

Abstract: Systems and techniques for distributed machine learning (DML) in an information centric network (ICN) are described herein. Finite message exchanges, such as those used in many DML exercises, may be efficiently implemented by treating certain data packets as interest packets to reduce overall network overhead when performing the finite message exchange. Further, network efficiency in DML may be improved achieved by using local coordinating nodes to manage devices participating in a distributed machine learning exercise. Additionally, modifying a round of DML training to accommodate available participant devices, such as by using a group quality of service metric to select the devices, or extending the round execution parameters to include additional devices, may have an impact on DML performance.

Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating an Enhanced Directional Multi-Gigabit (DMG) (EDMG) Physical Layer Protocol Data Unit (PPDU). For example, an EDMG wireless communication station (STA) may be configured to communicate an EDMG PPDU including a Channel Estimation Field (CEF) and/or a pilot sequence, which may be configured for an OFDM mode.

Abstract: A device and method for provided access to distributed data sources includes a cloud security server configured to associate any number of data sources and client devices with a cloud security server account. The cloud security server assigns trust levels to the data sources and the client devices. A client device requests data from the cloud security server. The cloud security server authenticates the client device and verifies the trust levels of the client device and the requested data. If verified, the cloud security server brokers a connection between the client device and the data source, and the client device accesses the requested data. Data sources may include cloud service providers and local storage devices. The cloud security server may assign a trust level to a client device for a limited time or revoke a trust level assigned to a client device. Other embodiments are described and claimed.

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

Abstract: A user equipment (UE) configured for operating in a fifth-generation (5G) new radio (NR) network may monitor search space sets for a number of physical downlink control channel (PDCCH) candidates within a number of non-overlapped control-channel elements (CCEs) for a primary cell (PCell). The number of PDCCH candidates and the number of non-overlapped CCEs may include PDCCH candidates and non-overlapped CCEs on a scheduling secondary cell (SCell). The scheduling SCell may be an SCell that schedules a transmission on the PCell. The UE may decode one or more of the PDCCH candidates on the scheduling SCell for a downlink control information (DCI) format which may schedule a physical downlink shared channel (PDSCH) transmission and/or a physical uplink shared channel (PUSCH) transmission of the PCell.

Abstract: A named function network (NFN) system includes a routing node, a function generation node, and a server node. The routing node receives requests for new functions, the requests including data values for generating the new functions. The function generation node receives the data values from the routing node and generates a new function for the NFN using the data values. The server node receives a request from the routing node to execute the new function, executes the new function, and transmits results of the execution to the routing node.

Abstract: Methods and apparatus for adaptive termination calibration of high-speed links. The methods provide a novel termination calibration obtained in conjunction with link training without using an external reference under which the termination resistors for transmitters (Rtx) and receivers (Rrx) are calibrated to the real channel impedance as part of the link training. The techniques may be implemented to optimize high-speed link operation in terms of impedance match between a channel's characteristic impedance and the source termination of a transmitter and the receiver termination of a receiver. During link training, both Rtx and Rrx are adjusted to maximize a peak amplitude of a received signal. Under one approach for bi-directional links, the Rrx for the receivers at both ends of the link are calibrated substantially concurrently. Under another approach, a calibrated Rrx for a first receiver is used for calibrating the Rrx for the second receiver.

Abstract: Managing scan detection of a component in a computing system includes detecting a scan interrupt, reading a scan register of the component, the scan register including a hashed identifier (ID) of the component; getting material vintage information of the component based at least in part on the hashed ID; and initiating a scan of the component based at least in part on the material vintage information to detect any defects in the component.

Abstract: In one example an apparatus comprises a first input node to receive a first plaintext input, a second input node to receive a random mask, an advanced encryption standard (AES) engine configurable to operate in one of a first mode in which the random mask is added to the first plaintext input during one or more computations performed by the AES engine, or second mode in which the random mask is not added to the first plaintext input during one or more computations performed by the AES engine. Other examples may be described.

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of vertically stacked dies; a trench of dielectric material through the plurality of vertically stacked dies; and a plurality of conductive vias extending through the trench of dielectric material, wherein individual ones of the plurality of conductive vias are electrically coupled to individual ones of the plurality of vertically stacked dies.

Abstract: Semiconductor structures having a source and/or drain with a refractory metal cap, and methods of forming the same, are described herein. In one example, a semiconductor structure includes a channel, a gate, a source, and a drain. The source and drain contain silicon and germanium, and one or both of the source and drain are capped with a semiconductor cap and a refractory metal cap. The semiconductor cap is on the source and/or drain and contains germanium and boron. The refractory metal cap is on the semiconductor cap and contains a refractory metal.

Abstract: An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

Abstract: An electronic device may include an interconnect bridge. The interconnect bridge may include a first electrical routing trace having a first routing length and a corresponding first transit time for a first electrical signal to transmit across the first routing length. The first electrical routing trace may transmit the first electrical signal along a major plane of the interconnect bridge between a first interconnect and a second interconnect. The interconnect bridge may include a routing trace deviation in communication with the first electrical routing trace. The routing trace deviation is outside a direct route between the first interconnect and the second interconnect. The routing trace deviation may alter one or more of capacitance or resistance of the first electrical routing trace and correspondingly alter the first routing time.

Abstract: Techniques for an instruction for a Runtime Call operation are described. An example apparatus comprises decoder circuitry to decode a single instruction, the single instruction to include a field for an identifier of an opcode, the opcode to indicate execution circuitry is to execute a no operation when a runtime call destination equals a predetermined value; and execute an indirect call with the runtime call destination as a destination address when the runtime call destination does not equal the predetermined value. Other examples are described and claimed.

Abstract: In one embodiment, an integrated circuit assembly includes a substrate comprising electrical connectors on a top side of the substrate and an integrated circuit die coupled to the top side of the substrate. The integrated circuit die includes metal pillars extending from a bottom side of the die facing the top side of the substrate, and the metal pillars of the integrated circuit die are electrically connected to the electrical connectors of the substrate via a liquid metal (e.g., a Gallium-based alloy).

Abstract: Stacked static random-access memory (SRAM) circuits have doubled word length for a given SRAM cell area. An integrated circuit (IC) die includes stacked SRAM cells in vertically adjacent device layers with access transistors connected to a common wordline. The IC die with stacked SRAM cells having a common word line may be attached to a substrate and coupled to a power supply and, advantageously, to an active-cooling structure. SRAM cells may be formed in vertically adjacent layers of a substrate and electrically connected at their access transistor gate electrodes.

Abstract: Integrated circuit dies, systems, and techniques are described herein related to three-dimensional dynamic random access memory. A memory device includes vertically aligned semiconductor structures coupled to independent gate structures, corresponding vertically aligned capacitors each coupled to a corresponding one of the semiconductor structures, and a bit line contact extending vertically across a depth of the semiconductor structures and coupled to each of the semiconductor structures.

Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.

Abstract: An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.

Abstract: An integrated circuit (IC) device package substrate comprises a plurality of first interconnect features to couple to a first IC die, a plurality of second interconnect features to couple to a second IC die, and one or more barrier features on a surface of the substrate. The first interconnect features span a first length in a first direction on the surface of the substrate. The second interconnect features span a second length in the first direction on the surface of the substrate. The second interconnect features are between the first length of the first interconnect features and a first edge of the substrate. The one or more barrier features are between the first and second interconnect features, wherein the one or more barrier features span a third length in the first direction, the third length greater than at least one of the first or second lengths.

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Abstract: Techniques related to bidirectional compact deep fusion networks for multimodal image inputs are discussed. Such techniques include applying a shared convolutional layer and independent batch normalization layers to input volumes for each modality and fusing features from the resultant output volumes in both directions across the modalities.

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Abstract: Memory arrays with backside components and angled transistors, and related assemblies and methods, are disclosed herein. A transistor is referred to as an “angled transistor” if a longitudinal axis of an elongated semiconductor structure of the transistor (e.g., a fin or a nanoribbon) is neither perpendicular nor parallel to any edges of front or back sides of a support structure (e.g., a die) over which the transistor is implemented. A component is referred to as a “backside component” if it is provided on the side of a semiconductor substrate that is opposite to the side over which the transistors of the memory arrays are provided. Memory arrays with backside components and angled transistors provide a promising way to increasing densities of memory cells on the limited real estate of semiconductor chips and/or decreasing adverse effects associated with continuous scaling of IC components.

Abstract: Integrated circuit dies, systems, and techniques are described herein related to one transistor-one capacitor dynamic random access memory. A memory device includes vertically aligned transistors having annular semiconductor structures and a shared bit line extending through the annular semiconductor structures, and vertically aligned capacitors having annular first capacitor plates, annular capacitor dielectric structures, and a shared second capacitor plate extending through the annular first capacitor plates, such that the annular first capacitor plates are in contact with corresponding ones of the annular semiconductor structures.

Abstract: Techniques and mechanisms for providing an integrated circuit (IC) which comprises an interconnect that extends between channel structures of two transistors. In an embodiment, a separation layer is provided between a first stack of channel structures and a second stack of channel structures, wherein an interior region of the separation layer comprises a sacrificial material which spans on overlap region between the stacks. Fabrication processes form a hole which exposes the interior region, and etching is performed to remove the sacrificial material from the separation layer. Subsequently, deposition processing forms in the interior region a trace portion of the interconnect. In another embodiment, the interconnect comprises a contiguous body of a conductor material, wherein the contiguous body extends to form respective regions of the trace portion, and a via portion of the interconnect.

Abstract: An integrated circuit (IC) device comprises a host component and an IC die directly bonded to the host component. The IC die comprises a substrate material layer and a die metallization level between the substrate material layer and host component. The IC die includes an upper die alignment fiducial between the die metallization level and host component. The upper die alignment fiducial at least partially overlaps one or more metallization features within the die metallization level. In embodiments, at least two orthogonal edges of the upper die alignment fiducial do not overlap any of the metallization features within the die metallization level. In embodiments, the IC die includes a lower die alignment fiducial between the substrate material layer and the die metallization level. The lower die alignment fiducial may at least partially overlap one or more second metallization features within a second die metallization level of the IC die.

Abstract: An integrated circuit includes an upper semiconductor body extending in a first direction from an upper source region to an upper drain region, and a lower semiconductor body extending in the first direction from a lower source region to a lower drain region. The upper body is spaced vertically from the lower body in a second direction orthogonal to the first direction. A gate spacer structure is adjacent to the upper and lower source regions. In an example, the gate spacer structure includes (i) a first section having a first dimension in the first direction, and (ii) a second section having a second dimension in the first direction. In an example, the first dimension is different from the second dimension by at least 1 nm. In some cases, an intermediate portion of the gate spacer structure extends laterally within a given gate structure, or between upper and lower gate structures.