Patents Examined by Aaron Gray
  • Patent number: 10204894
    Abstract: An integrated circuit layout includes a routing layout of routing conductors and routing connection vias formed prior to a power grid connection which forms power connection vias between power grid conductors and standard-power cell conductors within the standard cells. This enables a minimum via spacing requirement to be met while permitting an increased flexibility in the positioning of the routing connection vias.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: February 12, 2019
    Assignee: ARM Limited
    Inventor: Marlin Wayne Frederick, Jr.
  • Patent number: 10199386
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a first stacked body; a second stacked body being larger in number of stacked layers than the first stacked body, the second stacked body including a plurality of electrode layers separately stacked each other; a third stacked body being smaller in number of stacked layers than the first stacked body. The first stacked body includes a plurality of first layers separately stacked each other, and a plurality of second layers provided between the first layers. The third stacked body includes a third layer including a same material as the material of the first layers, and a fourth layer including a same material as the material of the second layers.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: February 5, 2019
    Inventors: Takashi Terada, Hisashi Kato, Noriaki Koyama
  • Patent number: 10181495
    Abstract: A process for producing a light emitting diode device, the process including: forming a plurality of quantum dots on a surface of a layer including a first area and a second area, the forming including: exposing the first area of the surface to light having a first wavelength while exposing the first area to a quantum dot forming environment that causes the quantum dots in the first area to form at a first growth rate while the quantum dots have a dimension less than a first threshold dimension; exposing the second area of the surface to light having a second wavelength while exposing the second area to the quantum dot forming environment that causes the quantum dots in the second area to form at a third growth rate while the quantum dots have a dimension less than a second threshold dimension; and processing the layer to form the LED device.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: January 15, 2019
    Assignee: X Development LLC
    Inventors: Martin Friedrich Schubert, Michael Jason Grundmann
  • Patent number: 10170549
    Abstract: Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: January 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Borna J. Obradovic, Robert C. Bowen, Mark S. Rodder
  • Patent number: 10170389
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Patent number: 10163725
    Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: December 25, 2018
    Inventors: Manoj Mehrotra, Charles Frank Machala, III, Rick L. Wise, Hiroaki Niimi
  • Patent number: 10128455
    Abstract: To increase emission efficiency of a fluorescent light-emitting element by efficiently utilizing a triplet exciton generated in a light-emitting layer. The light-emitting layer of the light-emitting element includes at least a host material and a guest material. The triplet exciton generated from the host material in the light-emitting layer is changed to a singlet exciton by triplet-triplet annihilation (TTA). The guest material (fluorescent dopant) is made to emit light by energy transfer from the singlet exciton. Thus, the emission efficiency of the light-emitting element is improved.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 13, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yusuke Nonaka, Satoshi Seo, Harue Osaka, Tsunenori Suzuki, Takeyoshi Watabe
  • Patent number: 10121906
    Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 10115732
    Abstract: Discrete silicon nitride portions can be formed at each level of electrically conductive layers in an alternating stack of insulating layers and the electrically conductive layers. The discrete silicon nitride portions can be employed as charge trapping material portions, each of which is laterally contacted by a tunneling dielectric portion on the front side, and by a blocking dielectric portion on the back side. The tunneling dielectric portions may be formed as discrete material portions or portions within a tunneling dielectric layer. The blocking dielectric portions may be formed as discrete material portions or portions within a blocking dielectric layer. The discrete silicon nitride portions can be formed by depositing a charge trapping material layer and selectively removing portions of the charge trapping material layer at levels of the insulating layers. Various schemes may be employed to singulate the charge trapping material layer.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: October 30, 2018
    Inventors: Jixin Yu, Zhenyu Lu, Daxin Mao, Yanli Zhang, Andrey Serov, Chun Ge, Johann Alsmeier
  • Patent number: 10109729
    Abstract: The present disclosure relates to a transistor device having a donor bi-layer configured to provide low-resistance to source and drain contacts while maintaining a high-mobility two-dimensional electron gas within a channel layer, and an associated method of formation. In some embodiments, the transistor device has a channel layer disposed over a substrate and a donor bi-layer disposed over the channel layer. The donor bi-layer includes a mobility-enhancing layer of AlzGa(1-z)N disposed over the channel layer and having a first molar fraction z in a first range, and a resistance-reducing layer of AlxGa(1-x)N disposed on and in contact with the mobility-enhancing layer of AlzGa(1-z)N and having a second molar fraction x in a second range less than the first range. Source and drain contacts are over the resistance-reducing layer of AlxGa(1-x)N. The donor bi-layer has a conduction band energy that monotonically decreases from top to bottom surfaces of the donor bi-layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chun Liu, Chung-Yi Yu, Chi-Ming Chen, Chen-Hao Chiang
  • Patent number: 10103178
    Abstract: A display device according to one embodiment, includes a thin-film transistor. The thin-film transistor includes a semiconductor layer including a channel region, first and second high-concentration impurity regions on both sides of the channel region, low-concentration impurity regions on both sides of the channel region, gate electrodes, first and second electrodes, and a light-shielding electrode opposing the channel region and the entire first high-concentration impurity region via an insulating layer, to produce a capacitance between itself and the first high-concentration impurity region.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: October 16, 2018
    Assignee: Japan Display Inc.
    Inventors: Masahiro Tada, Takashi Nakamura
  • Patent number: 10090470
    Abstract: A method of forming a semiconductor film at pressure between 10?5 atm and 10 atm in the presence of a substrate includes (i) providing a precursor material in a reaction container; (ii) arranging the substrate on the reaction container such that a conductive surface of the substrate is facing towards the precursor material; and (iii) conducting a heat treatment to deposit a semiconductor layer on the conductive surface of the substrate. A semiconductor film is obtained from this method and a device comprising such semiconductor film is also provided.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: October 2, 2018
    Inventors: Ruiqin Zhang, Juncao Bian
  • Patent number: 10090417
    Abstract: A p-type region, a p? type region, and a p+ type region are selectively disposed in a surface layer of a silicon carbide substrate base. The p-type region and the p? type region are disposed in a breakdown voltage structure portion that surrounds an active region. The p+ type region is disposed in the active region to make up a JBS structure. The p? type region surrounds the p-type region to make up a junction termination structure. A Schottky electrode forms a Schottky junction with an n-type silicon carbide epitaxial layer. The Schottky electrode overhangs an interlayer insulation film covering a portion of the p-type region and this overhanging portion acts as a field plate. The p+ type region has an acceptor concentration greater than or equal to a predetermined concentration and can make a forward surge current larger.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: October 2, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Tsuji, Akimasa Kinoshita, Noriyuki Iwamuro, Kenji Fukuda
  • Patent number: 10090198
    Abstract: Disclosed is a method for separating a substrate (1) along a separation pattern (4), in which method a substrate (1) is provided and an auxiliary layer (3) is applied to the substrate, said layer covering the substrate at least along the separation pattern. The substrate comprising the auxiliary layer is irradiated, such that the material of the auxiliary layer penetrates the substrate along the separation pattern in the form of an impurity. The substrate is broken along the separation pattern. A semiconductor chip (15) is also disclosed.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: October 2, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Mathias Kaempf
  • Patent number: 10090369
    Abstract: An organic light emitting diode display including a first connection line connected to an organic light emitting diode; a repair line intersecting the first connection line, the repair line being insulated from the first connection line; and a first welding part that is integrally formed with the first connection line or the repair line, the first welding part being aligned with an intersecting portion of the repair line and the first connecting line, and having a closed loop shape in plan view.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: October 2, 2018
    Inventors: Hwa-Jeong Kim, Chi Wook An
  • Patent number: 10090340
    Abstract: A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: October 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Olivier Plouchart, Devendra K. Sadana
  • Patent number: 10084080
    Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: September 25, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Qing Liu, John H. Zhang
  • Patent number: 10068844
    Abstract: A semiconductor device includes a molding compound and a through via extending through the molding compound. A via connection is disposed over the through via and a cap is disposed over the via connection. A plurality of holes are formed in a section of the cap.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Hsien-Wei Chen
  • Patent number: 10062678
    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: August 28, 2018
    Assignee: Micron Technologies, Inc.
    Inventors: Rich Fogal, Owen R. Fay
  • Patent number: 10062686
    Abstract: A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-connected distributed diode, where the base region is connected neither to the collector electrode nor to the emitter electrode. The bipolar transistor has unusually high emitter-to-base and emitter-to-collector reverse breakdown voltages. In the case of a PNP-type RBJT, an N base region extends into a P? epitaxial layer, and a plurality of P++ collector regions extend into the base region. Each collector region is annular, and rings a corresponding diode cathode region. Parts of the epitaxial layer serve as the emitter, and other parts serve as the diode anode. Insulation features separate metal of the collector electrode from the base region, and from P? type silicon of the epitaxial layer, so that the diode cathode is separated from the base region. This separation prevents base current leakage and reduces power dissipation during steady state on operation.
    Type: Grant
    Filed: January 22, 2017
    Date of Patent: August 28, 2018
    Assignee: IXYS, LLC
    Inventor: Kyoung Wook Seok