Abstract: A method for manufacturing an embedded chip package is provided. The method may include: forming electrically conductive lines over a substrate; placing the substrate next to a chip arrangement comprising a chip, the chip comprising one or more contact pads, wherein one or more of the electrically conductive lines are arranged proximate to a side wall of the chip; and forming one or more electrical interconnects over the chip arrangement to electrically connect at least one electrically conductive line to at least one contact pad.

Abstract: Methods and apparatus for determining substrate integrity and alignment are described. Devices as described herein can include a transfer chamber, one or more process chambers, a loadlock chamber a first optical device, a second optical device and a radiation source positioned outside and above an opening for the loadlock chamber. Methods as described herein can include delivering a substrate to an opening in a process chamber, activating the optical device and the radiation source and capturing a plurality of images, extracting a substrate edge pattern from the plurality of images, comparing the substrate edge pattern to an expected edge pattern to determine a level of edge variance and adjusting or stopping a process if the level of edge variance is outside of an edge variation range.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a high-k dielectric layer thereon; forming a first work function layer on the high-k dielectric layer; and forming a first oxygen-containing layer on the first work function layer.

Abstract: A method of reactive ion etching a substrate 46 to form at least a first and a second etched feature (42, 44) is disclosed. The first etched feature (42) has a greater aspect ratio (depth:width) than the second etched feature (44). In a first etching stage the substrate (46) is etched so as to etch only said first feature (42) to a predetermined depth. Thereafter in a second etching stage, the substrate (46) is etched so as to etch both said first and said second features (42, 44) to a respective depth. A mask (40) may be applied to define apertures corresponding in shape to the features (42, 44). The region of the substrate (46) in which the second etched feature (44) is to be produced is selectively masked with a second maskant (50) during the first etching stage, The second maskant (50) is then removed prior to the second etching stage.

Abstract: Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first conductive pillars and second conductive pillars respectively aligned to a first row of first pins and a second row of second pins of a first die, the first pins and the second pins differing in function; a first insulating layer covering surfaces of the first conductive pillars and the second conductive pillars facing away from the first die; first pads disposed on a surface of the first insulating layer facing away from the first die, the first pads substantially aligned to the first conductive pillars; and first traces coupled to the first pads, the first traces extending over a portion of the first insulating layer covering the second conductive pillars.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate including a transistor and a dummy gate disposed on the transistor, removing the dummy gate on the transistor, performing treatment using hydrogen (H2) on a surface of the semiconductor substrate, so as to remove residue materials left behind from the removal of the dummy gate, and forming a metal gate on the transistor.

Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

Abstract: The invention provides a thin film transistor, an array substrate and a display device. The thin film transistor comprises a conductive oxygen vacancy reducing layer for reducing oxygen vacancies in an active layer. The oxygen vacancy reducing layer is disposed between the active layer and a source and/or the active layer and a drain. With the oxygen vacancy reducing layer, the number of the oxygen vacancies in the active layer is decreased greatly, which improves transmission rate of carriers and simultaneously reduces value of subthreshold swing of the thin film transistor.

Abstract: An electro-optic device includes: a first substrate that includes a first surface; an optical element that is disposed in a first region on the first surface; a casing that is disposed to overlap with a part of the optical element along an outer periphery of the first region on the first surface and includes first and second end portions; a first resin layer that is disposed on an inside of the second end portion of the casing on the first surface and is installed to overlap with at least a part of the optical element; a second resin layer that is disposed on the first resin layer; and a second substrate that faces the first surface and is disposed on the second resin layer.

Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

Abstract: A Reverse Bipolar Junction Transistor (RBJT) integrated circuit comprises a bipolar transistor and a parallel-connected distributed diode, where the base region is connected neither to the collector electrode nor to the emitter electrode. The bipolar transistor has unusually high emitter-to-base and emitter-to-collector reverse breakdown voltages. In the case of a PNP-type RBJT, an N base region extends into a P? epitaxial layer, and a plurality of P++ collector regions extend into the base region. Each collector region is annular, and rings a corresponding diode cathode region. Parts of the epitaxial layer serve as the emitter, and other parts serve as the diode anode. Insulation features separate metal of the collector electrode from the base region, and from P? type silicon of the epitaxial layer, so that the diode cathode is separated from the base region. This separation prevents base current leakage and reduces power dissipation during steady state on operation.

Abstract: A semiconductor structure is provided that contains silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process feasibility. The semiconductor structure includes a first silicon fin of a first height and located on a pedestal portion of a first oxide structure. The structure further includes a second silicon fin of a second height and located on a pedestal portion of a second oxide structure. The first oxide structure and the second oxide structure are interconnected and the second oxide structure has a bottommost surface that is located beneath a bottommost surface of the first oxide structure. Further, the second height of the second silicon fin is greater than the first height of the first silicon fin, yet a topmost surface of the first silicon fin is coplanar with a topmost surface of the second silicon fin.

Abstract: One embodiment according to the present disclosure is an imaging apparatus including pixels. The pixel includes a junction type field effect transistor (JFET) provided in a semiconductor substrate. The JFET includes a gate region and a channel region. An orthogonal projection of the gate region onto a plane parallel to a surface of the semiconductor substrate intersects an orthogonal projection of the channel region onto the plane. Each of a source-side portion of the orthogonal projection of the channel region and a drain-side portion of the orthogonal projection of the channel region protrudes out of the orthogonal projection of the gate region.

Abstract: A semiconductor device capable of high speed operation is provided. Further, a semiconductor device in which change in electric characteristics due to a short channel effect is hardly caused is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed by self-aligned process in which one or more elements selected from Group 15 elements are added to the semiconductor layer with the use of a gate electrode as a mask. The source region and the drain region can have a wurtzite crystal structure.

Abstract: A method for producing an illuminant is specified, in which a positioning device (3) holds an optoelectronic semiconductor component (1) inside a tolerance range (4) on the upper side of a connection carrier (2) during the mechanical fixation and electrical connecting of the optoelectronic semiconductor component (1) to the connection carrier (2).

Abstract: In accordance with an embodiment, a semiconductor component and a method for manufacturing a semiconductor component are provided. A first dielectric material is formed over a body of semiconductor material of the first conductivity type and a plurality of semiconductor fingers are formed over the first of dielectric material. Semiconductor fingers of the plurality of semiconductor fingers spaced apart from each other and at least one of the semiconductor fingers has a first end spaced apart from a second end by a central region. A second dielectric material is formed over central region of the at least one semiconductor finger of the plurality of semiconductor fingers. An electrically conductive material is formed over the second dielectric material that is over the central region of the at least one semiconductor finger. The electrically conductive material serves as a shielding structure and the semiconductor material may be coupled to a fixed potential.

Abstract: A semiconductor structure includes an optoelectronic device located in one region of a substrate. A dielectric material is located adjacent and atop the optoelectronic device. A top contact is located within a region of the dielectric material and contacting a topmost surface of the optoelectronic device. A bottom metal contact is located beneath the optoelectronic device and lining a pair of openings located with other regions of the dielectric material, wherein a portion of the bottom metal contact contacts an entire bottommost surface of the optoelectronic device.

Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over a substrate and protruding out of the plane of substrate. A source region is disposed as a top portion of the frustoconical protrusion structure. A sidewall spacer is disposed along sidewall of the source region. A source contact with a critical dimension (CD), which is substantially larger than a width of the source region, is formed on the source region and the sidewall spacer together.

Abstract: A method for producing a plurality of optoelectronic components (100) comprises the steps: providing a semiconductor body (101) that is arranged on a carrier (114); and applying a converter material (105) to the semiconductor body (101) by means of a photoconductive transfer element (120).

Abstract: In an imaging device having a waveguide, a surface of an insulating film covering a seal ring is prevented from getting rough. A pixel region, a peripheral circuit region, and a seal region are defined over a semiconductor substrate. After formation of a pad electrode in the peripheral circuit region and a seal ring in the seal ring region, a TEOS film is so formed as to cover the pad electrode and the seal ring. A pattern of a photoresist for exposing a portion of the TEOS film covering the pad electrode and the seal ring, respectively, is formed and etching treatment is subjected to the exposed TEOS film. Then, after the pattern of the photoresist has been formed, a second waveguide holding hole is formed in the pixel region by performing etching treatment.