Abstract: An integrated circuit including a chip substrate having an upper isolation layer with a pad thereon and a coil located below the pad, where, in a dimension perpendicular to a surface of the chip substrate, a perimeter of the coil overlaps with a perimeter of the pad.

Abstract: A process for depositing titanium aluminum or tantalum aluminum thin films comprising nitrogen on a substrate in a reaction space can include at least one deposition cycle. The deposition cycle can include alternately and sequentially contacting the substrate with a vapor phase Ti or Ta precursor and a vapor phase Al precursor. At least one of the vapor phase Ti or Ta precursor and the vapor phase Al precursor may contact the substrate in the presence of a vapor phase nitrogen precursor.

Abstract: This disclosure relates to image sensors and electronic apparatuses including the same. An image sensor including: a pixel area including shared pixels, wherein each of the shared pixels includes at least two photodiodes that form a group and share a floating diffusion (FD) area; and a transistor (TR) area adjacent to the pixel area, wherein the TR area includes transistor sets corresponding to the shared pixels, wherein, when a first shared pixel and a second shared pixel are arranged adjacent to each other in a first direction, a first TR set corresponding to the first shared pixel and a second TR set corresponding to the second shared pixel share a source region of a first selection TR.

Abstract: A display apparatus includes: a first organic light-emitting diode, a second organic light-emitting diode, and a third organic light-emitting diode arranged on a substrate; a first intermediate layer commonly included in the first organic light-emitting diode and the second organic light-emitting diode, the first intermediate layer including a first emission layer and a first hole transport layer; a second intermediate layer included in the third organic light-emitting diode, the second intermediate layer including a second emission layer and a second hole transport layer; and a first color converting layer, a second color converting layer, and a third color converting layer. The first emission layer and the second emission layer are configured to emit different color lights from each other, and a hole mobility of the first hole transport layer is different from a hole mobility of the second hole transport layer.

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to the gate structure; performing a first cleaning process; performing a first rapid thermal anneal (RTA) process to remove oxygen cluster in the substrate; forming a metal layer on the source/drain region; and performing a second RTA process to transform the metal layer into a silicide layer.

Abstract: An organic light-emitting device includes: a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode, wherein the organic layer includes an emission layer, a first auxiliary layer, a second auxiliary layer, and an electron transport layer, the first auxiliary layer and the second auxiliary layer are disposed between the emission layer and the electron transport layer, the first auxiliary layer includes a first compound including a carbocyclic group that has three or more rings, and the second auxiliary layer includes: (i) a second compound that is a bipolar compound, (ii) a third compound that is a hole transport compound and a fourth compound that is an electron transport compound, or (iii) the second compound that is the bipolar compound and the fourth compound that is the electron transport compound.

Abstract: The subject disclosure is directed towards layered substrate structures with aligned optical access to electrical devices formed thereon for laser processing and electrical device tuning. According to an embodiment, a layered substrate structure is provided that comprises an optical substrate having a first surface and a second surface and a patterned bonding layer formed on the second surface that comprises a bonding region and an open region, wherein the open region exposes a portion of the second surface. The layered substrate structure further comprises a device chip bonded to the patterned bonding layer via the bonding region and comprising at least one electrical component aligned with the optical substrate and the open region. The at least one electrical component can include for example, a thin film wire, an air bridge, a qubit, an electrode, a capacitor or a resonator.

Abstract: Disclosed is a display device possessing: a substrate having a display region and a peripheral region surrounding the display region; a pixel over the display region; a passivation film over the pixel; a resin layer over the passivation film; a first dam over the peripheral region and surrounding the display region; and a second dam surrounding the first dam. The passivation film includes; a first layer containing an inorganic compound; a second layer over the first layer, the second layer containing an organic compound; and a third layer over the second layer, the third layer containing an inorganic compound. The second layer is selectively arranged in a region surrounded by the first dam. The resin layer is selectively arranged in a region surrounded by the second dam.

Abstract: A method of forming a semiconductor structure includes patterning a hard mask layer over a top surface of a substrate. The method also includes forming a first portion of one or more vertical fins below the patterned hard mask layer. The method further includes forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins. The method further includes forming a second portion of the one or more vertical fins in the substrate below the top spacer and trimming sidewalls of the second portion of the one or more vertical fins. The method further includes forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins. The one or more vertical fins provide one or more vertical transport channels for one or more vertical transport field-effect transistors.

Abstract: Systems and techniques that facilitate trimmable inductors for qubit frequency tuning are provided. In various embodiments, a device can comprise a Josephson junction. In various aspects, the Josephson junction can be shunted by a capacitor, and a trimmable inductor can couple the Josephson junction to a pad of the capacitor. In various cases, the trimmable inductor can comprise a first conductive path that includes a severable and/or weldable superconducting bridge and a second conductive path that is in parallel with the first conductive path. In various aspects, severing and/or welding the severable and/or weldable superconducting bridge can controllably change an inductance of the trimmable inductor, which can commensurately change a resonant frequency of a qubit formed by the Josephson junction and the capacitor.

Abstract: A semiconductor arrangement includes a first well formed to a first depth and a first width in a substrate and a second well formed to a second depth and a second width in the substrate. The first well is formed in the second well, the first depth is greater than the second depth, and the second width is greater than the first width. A source region is formed in the second well and a drain region is formed in the substrate.

Abstract: An interconnect clip includes a die attach pad that comp includes rises a die attach surface at an inner side of the interconnect clip, a heat dissipation pad that includes a heat dissipation surface at an outer side of the interconnect clip, and a lead contact pad that includes a lead contact surface at an inner side of the interconnect clip or at an outer side of the interconnect clip. The outer side of the interconnect clip in the lead contact pad faces and is spaced apart from the inner side of the interconnect clip in the heat dissipation pad, and the inner side of the interconnect clip in the lead contact pad faces and is spaced apart from the outer side of the interconnect clip in the die attach pad.

Abstract: An organic electroluminescence device according to an embodiment of the present disclosure includes a first electrode, a second electrode facing the first electrode, and a plurality of organic layers between the first electrode and the second electrode, wherein at least one organic layer of the plurality of organic layers includes a polycyclic compound containing two aromatic 6-membered rings which are linked by a single bond, and a plurality of benzimidazole groups which are substituted at the two aromatic 6-membered rings, wherein each of the two aromatic 6-membered rings includes a carbon atom or a nitrogen atom as an atom for forming a ring.

Abstract: Apparatus and methods for effective impurity gettering are described herein. In some embodiments, a described device includes: a substrate; a pixel region disposed in the substrate; an isolation region disposed in the substrate and within a proximity of the pixel region; and a heterogeneous layer on the seed area. The isolation region comprises a seed area including a first semiconductor material. The heterogeneous layer comprises a second semiconductor material that has a lattice constant different from that of the first semiconductor material.

Abstract: A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.

Abstract: The energy conversion performance, mechanical robustness, and cost associated with fabrication of a thermoelectric device may be improved by three-dimensional flexible thermoelectrics.

Abstract: Provided is a heterocyclic compound of Chemical Formula 1: wherein X1 is CR1 or N, X2 is CR2 or N, X3 is CR3 or N, X4 is CR4 or N, Y1 is CR5 or N, Y2 is CR6 or N, Y3 is CR7 or N, Y4 is CR8 or N, Z1 is CR9 or N, Z2 is CR10 or N, Z3 is CR11 or N, and Z4 is CR12 or N, wherein X1 to X4, Y1 to Y4 and Z1 to Z4 are not N at the same time; and at least one of R1 to R12 is Chemical Formula 2: wherein A1 is O, S or Se; L1 is a direct bond, or a substituted or unsubstituted arylene or heteroarylene group; at least one of Ar1 and Ar2 is a substituted or unsubstituted alkyl group, and the rest is a substituted or unsubstituted aryl or heteroaryl group; and the rest are the same as or different from each other, and each independently is hydrogen, deuterium, halogen, cyano, nitro, hydroxyl, carbonyl, ester, imide, amide, or a substituted or unsubstituted: alkyl, cycloalkyl, alkoxy, aryloxy, alkylthioxy, arylthioxy, alkylsulfoxy, arylsulfoxy, alkenyl, silyl, boron, amine, arylphosphine oxide, aryl, or heteroa

Abstract: A semiconductor device includes a substrate. The semiconductor device also includes a semiconductor layer disposed in the substrate. The semiconductor device further includes a first dielectric layer disposed on the semiconductor layer. The semiconductor device includes a second dielectric layer disposed on the first dielectric layer. The semiconductor device also includes a pair of thermopile segments disposed on the second dielectric layer. The first dielectric layer and the second dielectric layer form a chamber.

Abstract: An organic light-emitting display device includes quantum dots and an RGB color filter layer having quantum dots and thus is capable of removing 100% of interference among red, green, and blue color filters.

Abstract: An electrical fuse matrix includes a plurality of anti-fuse structures, a plurality of top metal plates, and a plurality of bottom metal plates. The anti-fuse structures are arranged in a matrix, and each of the anti-fuse structure includes a top conductive structure, a bottom conductive structure, and a dielectric film disposed between the top conductive structure and the bottom conductive structure. The anti-fuse structure has an hourglass shape. The top metal plates are disposed on the top conductive structures. The bottom metal plates are disposed on the bottom conductive structures.