Patents Examined by Aaron J Gray
  • Patent number: 10811551
    Abstract: A tandem solar cell includes a substrate a plurality of sub-cells stacked on the substrate and configured to sequentially perform photoelectric conversion with different wavelength band, and a metal disk array disposed on at least one of interfaces between adjacent sub-cells. A center wavelength of wavelength bands corresponding to the sub-cells gradually decreases as progressing downward with respect to an uppermost layer. The metal disk array reflects a light transmitting a sub-cell disposed over the metal disk array without being absorbed therein. The metal disk array is inserted by means of wafer bonding.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: October 20, 2020
    Assignee: Korea Research Institute of Standards and Science
    Inventors: Sang-Jun Lee, Jun-Oh Kim, Yeongho Kim, Sang-Woo Kang
  • Patent number: 10811316
    Abstract: A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ka Fai Chang, Fong-Yuan Chang, Chin-Chou Liu, Yi-Kan Cheng
  • Patent number: 10811413
    Abstract: Multi-voltage threshold vertical transport transistors and methods of fabrication generally include forming the transistors with vertically oriented silicon fin channels for both the n-type doped field effect transistors (nFET) and the p-type doped field effect transistors (pFET). A silicon oxynitride interfacial layer is provided on sidewalls of the fins in the nFET and a silicon dioxide interfacial with aluminum is provided on sidewalls of the fins in the pFET to provide an aluminum induced dipole. A high k dielectric overlays the interfacial layers and a common work function metal overlays the high k dielectric layer to define a gate structure.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 20, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Reinaldo Vega, Choonghyun Lee, Hari Mallela, Li-Wen Hung
  • Patent number: 10796971
    Abstract: A method of making a repaired electrical connection structure comprises providing a substrate having first and second contact pads electrically connected in parallel, providing first and second functionally identical components, disposing a first adhesive layer on the substrate, transferring the first component onto the first adhesive layer, electrically connecting the first component to the first contact pad, testing the first component to determine if the first component is a faulty component and, if the first component is a faulty component, disposing a second adhesive layer on the substrate and transferring the second component onto the second adhesive layer, and electrically connecting the second component to the second contact pad. The first and second adhesive layers can be unpatterned or patterned and the first and second components can be electrically connected to the first and second contact pads, respectively, with connection posts or photolithographically defined electrodes.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: October 6, 2020
    Assignee: X Display Company Technology Limited
    Inventors: Ronald S. Cok, Erich Radauscher, Salvatore Bonafede, Christopher Andrew Bower, Matthew Alexander Meitl, Carl Ray Prevatte, Jr., Brook Raymond
  • Patent number: 10797155
    Abstract: A semiconductor structure and a manufacturing method thereof are provided, wherein the semiconductor structure includes a substrate and gate structures. The gate structures are disposed on the substrate. Each of the gate structures includes a gate, a first spacer and a second spacer. The gate is disposed on the substrate. The first spacer is disposed on a sidewall of the gate. The second spacer is disposed on the first spacer. In a region between two adjacent gate structures, the first spacers are separated from each other, the second spacers are separated from each other, and an upper portion of each of the second spacers has a recess. The semiconductor structure can be used to form a good metal silicide.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: October 6, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Zhenhai Zhang
  • Patent number: 10784382
    Abstract: A PIN diode has an anode spaced away from a central region of a top surface of a substrate, such that the anode is in a corner or at a side edge of the top surface. Alternatively, the PIN diode has an anode surrounded by a shield layer. The PIN diode reduces unwanted parasitic capacitance to increase the reverse isolation of RF switches and to reduce the diffusion capacitance to increase the f3dB frequency specification of amplifier circuits. The PIN diode dramatically reduces the values of both parasitic and diffusion capacitances, which enables its application in switches and amplifiers under a wide variety of bias conditions including reverse, low-moderate forward, and large forward-bias; which enables bonding to a much larger metal area than the active electrode, with negligible increase in the parasitic capacitance; and which enables reliable wire-bonding by presenting a highly planar metal surface.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 22, 2020
    Inventors: Ashok T. Ramu, Robert J. Bayruns, Michel Francois
  • Patent number: 10784223
    Abstract: A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: September 22, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Chun Chuang, Chita Chuang, Chen-Shien Chen, Ming Hung Tseng
  • Patent number: 10741777
    Abstract: Provided is a stretchable display including an elastic body, a light emitting unit on the elastic body, and a wiring unit on the elastic body, wherein the light emitting unit includes a first substrate unit on the elastic body, a buffer layer on the first substrate unit, and a light emitting element on the buffer layer, the wiring unit includes a second substrate unit on the elastic body, a driving element configured to control the light emitting element, a wiring configured to electrically connect the driving element and the light emitting element, and an insulation layer configured to cover the driving element and the wiring, the light emitting unit and the wiring unit have respective corrugation structures, a thickness of the light emitting unit is larger than that of the wiring unit, a modulus of elasticity of the buffer layer is larger than that of the insulation layer, and a modulus of elasticity of the elastic body is smaller than that of the insulation layer.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 11, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Chi-Sun Hwang, Seung Youl Kang, Byoung-Hwa Kwon, Gi Heon Kim, Seong Hyun Kim, Jaehyun Moon, Young Sam Park, Seongdeok Ahn, Jeong Ik Lee, Sung Haeng Cho
  • Patent number: 10741468
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Patent number: 10741677
    Abstract: Embodiments of the present invention are directed to a method that incorporates a germanium pull-out process to form semiconductor structures having stacked silicon nanotubes. In a non-limiting embodiment of the invention, a sacrificial layer is formed over a substrate. The sacrificial layer includes a first type of semiconductor material. A pull-out layer is formed on the sacrificial layer. The first type of semiconductor material from the sacrificial layer is removed to form a silicon-rich layer on a surface of the sacrificial layer. The sacrificial layer can be removed such that the silicon-rich layer defines a silicon nanotube.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Choonghyun Lee, Peng Xu
  • Patent number: 10714625
    Abstract: A semiconductor device capable of high speed operation is provided. Further, a highly reliable semiconductor device is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed in such a manner that one or more of elements selected from rare gases and hydrogen are added to the semiconductor layer by an ion doping method or an ion implantation method with the use of a channel protective layer as a mask.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: July 14, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10700194
    Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: June 30, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Qing Liu, John H. Zhang
  • Patent number: 10700150
    Abstract: A unit pixel includes a circuit structure, first and second wiring patterns, an interlayer insulating layer, a planarization layer, and a light emission structure. The first wiring pattern disposed on the circuit structure has a first bump structure. The interlayer insulating layer covers the circuit structure and the first wiring pattern. The second wiring pattern disposed on the interlayer insulating layer overlaps the first wiring pattern and has a second bump structure. The planarization layer covers the interlayer insulating layer and the second wiring pattern and includes a via-hole exposing at least a portion of be second wiring pattern. The light emission structure contacts the second wiring pattern through the via-hole. The first and second wiring patterns and the interlayer insulating layer form a capacitor, the light emission structure includes an OLED, and the capacitor is directly connected to an anode of the OLED.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 30, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ilhun Seo, Yun-Mo Chung, Jae-Wook Kang, Hojin Yoon, Daewoo Lee, Minseong Yi, Tak-Young Lee, Miyeon Cho
  • Patent number: 10693089
    Abstract: The present disclosure relates to a flexible display device, including a flexible substrate. The substrate includes a first portion, a second portion and a bending portion connecting the first portion to the second portion, wherein the flexible substrate has a thickness T. A plurality of display pixels is located at a side of the first portion of the flexible substrate. A supporting layer is located at a side of the flexible substrate facing away from the plurality of display pixels and includes a first supporting layer corresponding to the first portion and a second supporting area corresponding to the second portion. A thickness of the first supporting layer is T1, a thickness of the second supporting layer is T2, and a width of the bending portion is W, wherein W ? ( 2 ? T + T ? ? 1 + T ? ? 2 ) ? ? 2 . Therefore, a narrow border is achieved, and the problem of interference during bending is alleviated.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: June 23, 2020
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yongxin He, Dong Chang, Donghua Chen, Zhenying Li
  • Patent number: 10658300
    Abstract: A semiconductor package includes a lower chip, an upper chip on the lower chip, and an adhesive layer between the lower chip and the upper chip. The lower chip has first through silicon vias (TSVs) and pads on an upper surface thereof. The pads are connected to the first TSVs, respectively. The upper chip includes bumps on a lower surface thereof. The bumps are bonded to the pads. Vertical centerlines of the bumps are aligned with vertical centerlines of the first TSVs, respectively. The vertical centerlines of the bumps are offset from the vertical centerlines of the pads, respectively, in a peripheral region of the lower chip.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Lyong Kim, Seung-Duk Baek
  • Patent number: 10658628
    Abstract: An organic light emitting display device includes a substrate. A buffer layer is disposed on the substrate. The buffer layer includes a first opening exposing an upper surface of the substrate in a bending region. Pixel structures are positioned in a pixel region on the buffer layer. A fan-out wiring is positioned in the peripheral region and the pad region on the insulation layer structure such that the upper surface of the substrate and the first portion of the buffer layer are exposed. A passivation layer is disposed on the fan-out wiring, side walls of the insulation layer structure adjacent to the bending region, and the first portion of the buffer layer. The passivation layer includes a third opening exposing the upper surface of the substrate in the bending region. A connection electrode is positioned in the bending region on the substrate.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: May 19, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jeongho Lee, Yanghee Kim, Juncheol Shin, Hokyoon Kwon, Deukjong Kim, Keunsoo Lee
  • Patent number: 10658439
    Abstract: Disclosed is a display device possessing: a substrate having a display region and a peripheral region surrounding the display region; a pixel over the display region; a passivation film over the pixel; a resin layer over the passivation film; a first dam over the peripheral region and surrounding the display region; and a second dam surrounding the first dam. The passivation film includes; a first layer containing an inorganic compound; a second layer over the first layer, the second layer containing an organic compound; and a third layer over the second layer, the third layer containing an inorganic compound. The second layer is selectively arranged in a region surrounded by the first dam. The resin layer is selectively arranged in a region surrounded by the second dam.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: May 19, 2020
    Assignee: Japan Display Inc.
    Inventor: Jun Hanari
  • Patent number: 10651416
    Abstract: A display device including a substrate including a light emission area and a non-light emission area, a pixel defining layer disposed in the non-light emission area, the pixel defining layer defining the light emission area, a first electrode disposed in the light emission area, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer, in which the second electrode includes a first metal layer and a second metal layer disposed on the first metal layer, and the second metal layer has an aperture disposed at an edge portion of the light emission area.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: May 12, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Junyoung Kim
  • Patent number: 10651270
    Abstract: In a semiconductor device having a first p+-type base region, a second p+-type base region, a high-concentration n-type region selectively formed in an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate; a p-type base layer formed on the n-type silicon carbide epitaxial layer; an n+-type source region and a p++-type contact region selectively formed in a surface layer of the p-type base layer; and a trench formed penetrating the p-type base layer and shallower than the second p+-type base region, in at least a part of the first p+-type base region, a region is shallower than the second p+-type base region as viewed from an element front surface side.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: May 12, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Yusuke Kobayashi, Shinsuke Harada, Yasuhiko Oonishi
  • Patent number: 10651215
    Abstract: The present invention relates to a sensor system. The sensor system comprises a component carrier and a sensor having a control unit and a sensor unit. At least a part of the sensor unit is located within the component carrier.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 12, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Mikael Tuominen