Abstract: A method of forming an image sensor includes forming a first image sensor element within a substrate. The first image sensor element and the substrate respectively comprise a first material. A second image sensor element is formed within the substrate. Forming the second image sensor element includes forming an isolation layer over the first image sensor element. Further, a buffer layer is formed over the isolation layer and an active layer is formed over the buffer layer. The active layer comprises a second material different from the first material.

Abstract: A phase-transition optical isomer compound is described, a transparent EL display device including the phase-transition optical isomer compound and a method of fabricating the EL display device, where a phase of the phase-transition optical isomer compound is transited by light irradiation and a second electrode of the EL display device is selectively deposited without a masking process.

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Abstract: A method of manufacturing a semiconductor structure includes depositing a silicon layer over a substrate, removing a portion of the silicon layer to form a gate stack, and performing a hydrogen treatment on the gate stack to repair a plurality of voids in the stack structure.

Abstract: An integrated circuit (IC) package comprising an IC die, the IC die having a first surface and an opposing second surface. The IC die comprises a semiconductor material. The first surface comprises an active layer. A thermoelectric cooler (TEC) comprising a thermoelectric material is embedded within the IC die between the first surface and the second surface and adjacent to the active layer. The TEC has an annular shape that is substantially parallel to the first and second surfaces of the IC die. The thermoelectric material is confined between an outer sidewall along an outer perimeter of the TEC and an inner sidewall along an inner perimeter of the TEC. The outer and inner sidewalls are substantially orthogonal to the first and second surfaces of the IC die.

Abstract: A method includes providing dummy gate structures disposed over a device region and over an isolation region adjacent the active region, first gate spacers disposed along sidewalls of the dummy gate structures in the active region, and second gate spacers disposed along sidewalls of the dummy gate structures in the isolation region, removing top portions of the second, but not the first gate spacers, forming a first dielectric layer over the first gate spacers and remaining portions of the second gate spacers, replacing the dummy gate structures with metal gate structures after the forming of the first dielectric layer, removing the first gate spacers after the replacing of the dummy gate structures, and forming a second dielectric layer over top surfaces of the metal gate structures and of the first dielectric layer.

Abstract: An integrated circuit structure includes a substrate, a metal ring penetrating through the substrate, a dielectric region encircled by the metal ring, and a through-via penetrating through the dielectric region. The dielectric region is in contact with the through-via and the metal ring.

Abstract: Provided are opto-electronic devices with low dark noise and high signal-to-noise ratio and methods of manufacturing the same. An opto-electronic device may include: a semiconductor substrate; a light receiving unit formed in the semiconductor substrate; and a driving circuit arranged on a surface of the semiconductor substrate. The light receiving unit may include: a first semiconductor layer partially arranged in an upper region of the semiconductor substrate and doped with a first conductivity type impurity; a second semiconductor layer arranged on the first semiconductor layer and doped with a second conductivity type impurity; a transparent matrix layer arranged on an upper surface of the second semiconductor layer; a plurality of quantum dots arranged to contact the transparent matrix layer; and a first electrode and a second electrode electrically connected to the second semiconductor layer and respectively arranged on both sides of the transparent matrix layer.

Abstract: Self-organizing patterns with micrometer-scale feature sizes are promising for the large area fabrication of photonic devices and scattering layers in optoelectronics. Pattern formation would ideally occur in the active semiconductor to avoid the need for further processing steps. The present disclosure includes approaches to form period patterns in single layers of organic semiconductors by an annealing process. When heated, a crystallization front propagates across the film, producing a sinusoidal surface structure with wavelengths comparable to that of near-infrared light. These surface features form initially in the amorphous region within a micron of the crystal growth front, likely due to competition between crystal growth and surface mass transport. The pattern wavelength can be tuned by varying film thickness and annealing temperature, millimeter scale domain sizes are obtained. Aspects of the disclosure can be exploited for self-assembly of microstructured organic optoelectronic devices, for example.

Abstract: The present invention relates to the manufacture of Josephson junctions. Such Josephson junctions may be suitable for use in qubits. High-quality, potentially monocrystalline, electrode and dielectric layers are formed using blanket deposition. Subsequently, the structure of one of more Josephson junctions is formed using multi-photon lithography to create openings in a resist followed by etching the electrode and dielectric layers.

Abstract: An electrical fuse matrix includes a plurality of anti-fuse structures, a plurality of top metal plates, and a plurality of bottom metal plates. The anti-fuse structures are arranged in a matrix, and each of the anti-fuse structure includes a top conductive structure, a bottom conductive structure, and a dielectric film disposed between the top conductive structure and the bottom conductive structure. The anti-fuse structure has an hourglass shape. The top metal plates are disposed on the top conductive structures. The bottom metal plates are disposed on the bottom conductive structures.

Abstract: The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region.

Abstract: A one time programmable memory device includes a field effect transistor and an antifuse structure. A first node of the antifuse structure includes, or is electrically connected to, the drain region of the field effect transistor. The antifuse structure includes an antifuse dielectric layer and a second node on, or over, the antifuse dielectric layer. One of the first node and the second node includes the drain region or a metal via structure formed within a via cavity extending through an interlayer dielectric material layer that overlies the field effect transistor.

Abstract: According to an aspect, a sensor packaging structure includes a sensor die having a first surface and a second surface opposite the first surface, where the sensor die defines a sensor edge disposed between the first surface and the second surface. The sensor packaging structure includes a bonding material having a first surface and a second surface opposite the second surface, where the bonding material defines a bonding material edge disposed between the first surface of the bonding material and the second surface of the bonding material. The sensor packaging structure includes a transparent material, where the bonding material couples the sensor die to the transparent material. The sealing material is disposed on an interface between the sensor die and the bonding material, and at least one of a portion of the sensor edge or a portion of the bonding material edge.

Abstract: A die ejection apparatus operable to eject a die from a support has at least two ejector components configured to lift a die located on the support. The ejector components are moveable to a position in which a lifting force is exertable by the ejector components on the support, so as to lift a die located on the support. Movement of the die ejector components is initiated towards the support, and a moment when each of the die ejector components reaches the position is determined. A height offset of each die ejector component relative to a height of another die ejector component is determined upon reaching the said position, and relative heights of the die ejector components are adjusted in dependence upon the evaluated height offset.

Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.

Abstract: The present disclosure provides an organic light emitting diode device and a manufacturing method thereof, a display panel and a display device. The organic light emitting diode device includes: a substrate; and a light emitting component and a first structural layer provided on a side of the substrate, wherein the light emitting component is provided on a side of the first structural layer distal to the substrate, and a light emitting surface of the light emitting component comprises a curved surface recessed towards the substrate, and the curved surface comprises a spherical-cap curved surface or a concave-convex curved surface which is constituted by a plurality of spherical-cap curved surfaces.

Abstract: An optoelectronic device including: a first circuit including a substrate having first and second opposite faces, the first circuit having display pixels, each display pixel having, on the side of the first face, a first light-emitting diode having a first active region adapted to emit a first radiation and, extending from the second face, a second light-emitting diode having a second active region adapted to emit a second radiation, the surface area, viewed from a direction orthogonal to the first face, of the first active region being at least twice as big as the surface area, viewed from the direction, of the second active region; and a second circuit bonded to the first circuit on the side of the first light-emitting diode and electrically linked to the first and second light-emitting diodes.

Abstract: A display panel, methods for manufacturing and detecting the display panel and a display device are provided. The display panel includes: a substrate, including a display region and a circuit region; multiple signal line terminals in the circuit region, coupled with signal lines respectively; multiple switch elements in the circuit region, first terminals of the switch elements are coupled with the signal line terminals respectively; multiple leads located in the circuit region and on a side of the signal line terminals distal to the display region, spaced apart from each other along a first direction, extending along a second direction, first ends of the leads are coupled with the second terminals of the switch elements respectively, second ends of the leads in the second direction extend to an edge of the substrate, each switch element is configured to connect or disconnect the first terminal and the second terminal thereof.

Abstract: The invention discloses a dynamic random access memory (DRAM) device and a method of fabricating such DRAM device. The DRAM device according to the invention includes a plurality of bit lines formed on a semiconductor substrate, a plurality of first isolation stripes, a plurality of second isolation stripes, a plurality of transistors formed between the first isolation stripes and the second isolation stripes, a plurality of word lines, and a plurality of capacitors formed above the first isolation stripes and the second isolation stripes. The semiconductor substrate defines a longitudinal direction, a transverse direction, a normal direction, a plurality of columns in the longitudinal direction, and a plurality of rows in the transverse direction. The first isolation stripes and the second isolation stripes extend in the longitudinal direction. Each transistor corresponds to one of the columns and one of the rows.