Abstract: A semiconductor apparatus includes: a semiconductor substrate; a diffusion layer; a first depletion prevention region; a channel stopper electrode, a monitor electrode and an insulating film. The inner edge portion of the monitor electrode is positioned between the diffusion layer and the first depletion prevention region. A distance between the outer edge portion of the channel stopper electrode and the inner edge portion of the monitor electrode is a first distance. A distance between the diffusion layer and the first depletion prevention region is a second distance. The first and second distances are set so that a discharge voltage between the channel stopper electrode and the monitor electrode becomes greater than an avalanche breakdown voltage at a PN junction portion of the diffusion layer and the semiconductor substrate.

Abstract: Disclosed herein is a display panel, comprising: a support; a first layer comprising a light emitter, a first region and a second region; a second layer sandwiched between the first layer and the support; wherein the first region and the second region allow light scattered by an object (e.g., a person's finger) to transmit therethrough; wherein the second layer allows light transmitted through the first region to reach the support and comprises a light-blocking layer configured to attenuate light transmitted through the second region.

Abstract: A material deposition system comprises a dopant source containing at least one dopant precursor material, an inert gas source containing at least one noble gas, and a physical vapor deposition apparatus in selective fluid communication with the dopant source and the inert gas source. The physical vapor deposition apparatus comprises a housing structure, a target electrode, and a substrate holder. The housing structure is configured and positioned to receive at least one feed fluid stream comprising the at least one dopant precursor material and the at least one noble gas. The target electrode is within the housing structure and is in electrical communication with a signal generator. The substrate holder is within the housing structure and is spaced apart from the target electrode. A method of forming a microelectronic device, a microelectronic device, a memory device, and an electronic system are also described.

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

Abstract: The present disclosure provides a method for manufacturing an array substrate, an array substrate, and a display device. By first forming holes in a first thin film transistor, then simultaneously performing hydrogen supplementation on the first thin film transistor and a second thin film transistor, and then forming holes in the second thin film transistor, the first thin film transistor and the second thin film transistor can be repaired and compensated in different degrees by hydrogen supplementation.

Abstract: A semiconductor device according to an embodiment includes, a silicon carbide layer having first and second planes; a first electrode on the first plane; a second electrode on the second plane; a first conductivity type first silicon carbide region; second and third silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane; a first conductivity type fifth silicon carbide region between the first and the second silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type sixth silicon carbide region between the first and the third silicon carbide region with higher impurity concentration than the first silicon carbide region; a first conductivity type seventh silicon carbide region between the fifth and the sixth silicon carbide region with lower impurity concentration than the fifth and the sixth silicon carbide region; and a gate electrode.

Abstract: A display substrate having a plurality of subpixels is provided. The display substrate includes a base substrate; and a pixel definition layer defining a plurality of subpixel apertures. The pixel definition layer includes a smart material sub-layer comprising a smart insulating material. The display substrate in a respective one of the plurality of subpixels includes an organic light emitting layer in a respective one of the plurality of subpixel apertures.

Abstract: Systems and techniques providing suitable chip structures for facilitating antenna-based thermal annealing of qubits are provided. In one example, a radio frequency emitter can comprise a voltage-controlled oscillator and an antenna. The voltage-controlled oscillator can receive power-on signals from a microcontroller, thereby causing the voltage-controlled oscillator to generate an electromagnetic wave. The antenna can then direct the electromagnetic wave onto a set of one or more capacitor pads of a Josephson junction on a superconducting qubit chip, thereby annealing the Josephson junction. In another example, a voltage regulator and a digital-to-analog converter or digital-to-digital converter can be coupled in series between the microcontroller and the voltage-controlled oscillator, thereby allowing the voltage-controlled oscillator to be voltage and/or frequency tunable and eliminating the need for external power routing as compared to photonic laser annealing.

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

Abstract: A floating base silicon controlled rectifier is provided, which at least comprises a first conductivity type layer; a second conductivity type well formed in the first conductivity type layer; a first conductivity type heavily doped region coupled to a first node and formed in the second conductivity type well; and a second conductivity type heavily doped region coupled to a second node and formed in the first conductivity type layer. The first conductivity type and the second conductivity type are opposite. When the first conductivity type is N type, the second conductivity type is P type. Alternatively, when the first conductivity type is P type, the second conductivity type is N type. By employing the proposed present invention, the floating base silicon controlled rectifier acts as a forward diode, and an input capacitance can be greatly reduced.

Abstract: Provided is a display panel including a display area, which includes an optical component arrangement region including a light-blocking region and light-transmitting region units distributed in rows and columns. Each light-transmitting region unit includes first and second sets of light-transmitting regions that are arranged along a first direction. The first set of light-transmitting regions includes a first light-transmitting region and a second light-transmitting region arranged along a second direction, and the second set of light-transmitting region includes a third light-transmitting region and a fourth light-transmitting region arranged along the second direction. The first direction intersects with the second direction. Each light-transmitting region has a length direction. An angle formed between the length direction and the first direction is within a range of 10° to 40°.

Abstract: A display device includes: a substrate on which a plurality of sub-pixels are arranged; a light-emitting device including a light-emitting layer in each of the plurality of sub-pixels; a thin film encapsulation layer covering the light-emitting layer in each of the plurality of sub-pixels; a black matrix around the plurality of sub-pixels; and an optical sensor on the substrate, the optical sensor including a sensing portion for sensing light emitted from a light source, wherein the black matrix has a plurality of openings, through which light emitted from the light source passes, in a path through which the light is received by the sensing portion via an input object which is in contact with the substrate.

Abstract: To increase emission efficiency of a fluorescent light-emitting element by efficiently utilizing a triplet exciton generated in a light-emitting layer. The light-emitting layer of the light-emitting element includes at least a host material and a guest material. The triplet exciton generated from the host material in the light-emitting layer is changed to a singlet exciton by triplet-triplet annihilation (TTA). The guest material (fluorescent dopant) is made to emit light by energy transfer from the singlet exciton. Thus, the emission efficiency of the light-emitting element is improved.

Abstract: Nanocomposites in accordance with many embodiments of the invention can be capable of converting electromagnetic radiation to an electric signal, such as signals in the form of current or voltage. In some embodiments, metallic nanostructures are integrated with graphene material to form a metallo-graphene nanocomposite. Graphene is a material that has been explored for broadband and ultrafast photodetection applications because of its distinct optical and electronic characteristics. However, the low optical absorption and the short carrier lifetime of graphene can limit its use in many applications. Nanocomposites in accordance with various embodiments of the invention integrates metallic nanostructures, such as (but not limited to) plasmonic nanoantennas and metallic nanoparticles, with a graphene-based material to form metallo-graphene nanostructures that can offer high responsivity, ultrafast temporal responses, and broadband operation in a variety of optoelectronic applications.

Abstract: A poly-insulator-poly (PIP) capacitor including a substrate having a capacitor forming region; a first capacitor dielectric layer on the capacitor forming region; a first poly electrode on the first capacitor dielectric layer; a second capacitor dielectric layer on the first poly electrode; and a second poly electrode on the second capacitor dielectric layer. A third poly electrode is disposed adjacent to a first sidewall of the second poly electrode. A third capacitor dielectric layer is disposed between the third poly electrode and the second poly electrode. A fourth poly electrode is disposed adjacent to a second sidewall of the second poly electrode opposite to the first sidewall. A fourth capacitor dielectric layer is disposed between the fourth poly electrode and the second poly electrode.

Abstract: Disclosed is a method of fabricating a stretchable electronic device, the method including a step of forming one or more semiconductor devices on a first carrier substrate; a step of forming semiconductor device array patterns by separating semiconductor device arrays each including the semiconductor devices; a step of releasing the semiconductor device array patterns from the first carrier substrate; a step of forming a stretchable substrate on a second carrier substrate; and a step of transferring the released semiconductor device array patterns onto the stretchable substrate.

Abstract: A display panel and a method of manufacturing thereof are provided. The method of manufacturing a display panel includes forming a driving circuit on a substrate; forming an electrode, including a first area and a second area therewith, on the driving circuit; mounting a first micro Light Emitting Diode (LED), for forming a sub pixel, on the first area; forming an absorption layer on the second area, the absorption layer configured to absorb an external light; removing, based on the sub pixel being defective, the absorption layer; and mounting a second micro LED on the second area after removing the absorption layer.

Abstract: A semiconductor device capable of high speed operation is provided. Further, a highly reliable semiconductor device is provided. An oxide semiconductor having crystallinity is used for a semiconductor layer of a transistor. A channel formation region, a source region, and a drain region are formed in the semiconductor layer. The source region and the drain region are formed in such a manner that one or more of elements selected from rare gases and hydrogen are added to the semiconductor layer by an ion doping method or an ion implantation method with the use of a channel protective layer as a mask.

Abstract: A method for wafer planarization includes forming a second insulating layer and a polishing layer on a substrate having a chip region and a scribe lane region; forming a first through-hole in the polishing layer in the chip region and the scribe lane region and a second through-hole in the second insulating layer in the chip region, wherein the second through-hole and the first through-hole meet in the chip region; forming a pad metal layer inside the first through-hole and the second through-hole and on an upper surface of the polishing layer; and polishing the polishing layer and the pad metal layer by a chemical mechanical polishing (CMP) process to expose an upper surface of the second insulating layer in the chip region and the scribe lane region.

Abstract: A system includes a quantum processor includes a plurality of qubits. For each qubit, there is a circulator operative to receive a control signal and an output signal from the qubit. An isolator is coupled to an output of the circulator. A quantum-limited amplifier is coupled to an output of the isolator and configured to provide an output of the qubit. A multiplexor (MUX) is configured to frequency multiplex the outputs of at least two of the plurality of qubits as a single output of the quantum processor.