Abstract: Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug.

Abstract: This disclosure discloses a light-emitting element having a light-emitting unit, a transparent layer and a wavelength conversion layer formed on the transparent layer. The transparent layer covers the light-emitting unit. The wavelength conversion layer includes a phosphor layer having a phosphor and a stress release layer without the phosphor.

Abstract: An active device array substrate includes a substrate, first and second active devices, a gate insulation layer and an insulation barrier layer. The first and second active devices respectively includes first and second gate electrodes, first and second semiconductor blocks, first and second source electrodes, and first and second drain electrodes. A film layer of the second source electrode and the second drain electrode is the same with that of the first source electrode or the first drain electrode. The gate insulation layer is located between the first gate electrode and the first semiconductor block and between the second gate electrode and the second semiconductor block. The insulation barrier layer is disposed on the gate insulation layer, and covers the first semiconductor block. The insulation barrier layer has a first through hole for one of the first source electrode and the first drain electrode contacting the first semiconductor block.

Abstract: A method of manufacturing a light emitting device includes: providing a substantially flat plate-shaped base member which in plan view includes at least one first portion having an upper surface, and a second portion surrounding the at least one first portion and having inner lateral surfaces; mounting at least one light emitting element on the at least one first portion; shifting a relative positional relationship between the at least one first portion and the second portion in an upper-lower direction to form at least one recess defined by an upper surface of the at least one first portion that serves as a bottom surface of the at least one recess and at least portions of the inner lateral surfaces of the second portion that serve as lateral surfaces of the at least one recess; and bonding the at least one first portion and the second portion with each other.

Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

Abstract: In one disclosed embodiment, a non-volatile memory cell is constructed using a floating gate transistor with a channel that includes a buried channel region interposed between two surface channel regions under a floating gate. The surface channel regions are formed using angled lightly-doped drain implantation at locations in the substrate so that a first surface channel region is located under a first end of the floating gate and a second surface channel region is located under a second end of the floating gate. In one embodiment, the floating gate transistor is a PMOS transistor, with the channel being formed in an n-well formed in a p-type substrate, with the buried channel region being formed using a Vtp implant, and with the surface channel regions being formed using angled NLDD implants. The surface channel regions increase the energy barrier along the channel and reduce off state current of the memory cell.

Abstract: An anti-fuse device includes: a well region disposed in a semiconductor substrate; a gate electrode disposed on a gate insulating film on the semiconductor substrate; and a first well bias tap region disposed below the gate insulating film and the gate electrode in the well region, wherein the well bias tap region is doped with dopants of a same conductivity type as the well region.

Abstract: A second protective film is formed by applying high-viscosity resin by an inkjet method, in two patterns that extend parallel to and along a boundary between a first protective film and a plating film, the boundary being sandwiched between the two patterns. A low-viscosity resin is applied between these first and second patterns of the second protective film by the inkjet method. The low-viscosity resin has a viscosity that is lower than that of the high-viscosity resin for forming the second protective film, and a fluidity that is higher than that of the high-viscosity resin and thus, leaks and spreads into a gap between the first protective film and the plating film. The third protective film adheres to the first and second patterns, is formed across the boundary between the first protective film and the plating film, and is embedded in the gap whereby the gap is plugged.

Abstract: Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.

Abstract: A power semiconductor device includes a semiconductor body coupled to first and second load terminal structures, an active cell field in the body, and a plurality of first and second cells in the active cell field. Each cell is electrically connected to the first load terminal structure and to a drift region. Each first cell includes a mesa having a port region electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each second cell includes a mesa having a port region of the opposite conductivity type electrically connected to the first load terminal structure, and a channel region coupled to the drift region. Each mesa is spatially confined in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and has a total extension of less than 100 nm in the direction.

Abstract: A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are adjacent and within the same dielectric level; an air gap structure in the dielectric layer and between the first metal line and the second metal line, wherein the air gap structure includes an air gap oxide layer and an air gap; and a barrier layer between the air gap structure and the first metal line, wherein the barrier layer is an oxidized metal layer.

Abstract: A display device includes a substrate having a light emission area and a non-light emission area, a pixel defining layer disposed in the non-light emission area, the pixel defining layer defining the light emission area, a first electrode disposed in the light emission area, a light emitting layer disposed on the first electrode, and a second electrode disposed on the light emitting layer, in which the second electrode includes a first transmission portion in the light emission area and a second transmission portion on an edge portion of the light emission area, the second transmission portion surrounding the first transmission portion, and the second transmission portion has a light transmittance greater than a light transmittance of the first transmission portion.

Abstract: Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines.

Abstract: A display apparatus may include a substrate. The display apparatus may further include a display unit that includes an emission layer and is disposed on the substrate. The display apparatus may further include a protective layer that overlaps the display unit. The display apparatus may further include an organic layer that is disposed between the display unit and the protective layer. A top surface area of the organic layer may be equal to or less than a top surface area of the protective layer.

Abstract: A filling material for a resin composition includes a base material and a coating material coating at least a portion of a surface of a particle of the base material. The base material comprises a first inorganic compound containing a Group II element. The coating material comprises a second inorganic compound containing the Group II element and is different from the first inorganic compound. A method of manufacturing the filling material is provided. A resin composition comprising the filling material, a package, a light-emitting device, and methods of manufacturing them are also provided.

Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a metal-containing compound over the work function tuning layer, and a metal over the metal-containing compound, wherein the metal-containing compound comprises the metal as an element of the compound.

Abstract: A fan-out semiconductor package includes: a semiconductor chip having an active surface with connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the active surface of the semiconductor chip, wherein the encapsulant is a cured photosensitive resin composition including a thermosetting resin, a carboxylic resin, an ethylenically unsaturated compound, and a reinforcing agent. The photosensitive resin composition may be used in the fan-out semiconductor package.

Abstract: Semiconductor devices and methods of making semiconductor devices with a barrier layer comprising manganese nitride are described. Also described are semiconductor devices and methods of making same with a barrier layer comprising Mn(N) and, optionally, an adhesion layer.

Abstract: Disclosed is an ejection volume compensation method of an inkjet printer for manufacturing an organic electroluminescent device pixel. The inkjet printer includes a plurality of nozzles and is configured to perform a plurality of print processes for the same pixel location. A target ejection volume for the next print process is selected so that an average of the target ejection volume and an actual ejection volume for the previous print process is equal to an ideal ejection volume. Also disclosed are an ejection volume compensation device for use with the inkjet printer, an inkjet printing device, and a non-transitory machine readable medium.