Abstract: The present invention relates to a sensor system. The sensor system comprises a component carrier and a sensor having a control unit and a sensor unit. At least a part of the sensor unit is located within the component carrier.

Abstract: A process for depositing titanium aluminum or tantalum aluminum thin films comprising nitrogen on a substrate in a reaction space can include at least one deposition cycle. The deposition cycle can include alternately and sequentially contacting the substrate with a vapor phase Ti or Ta precursor and a vapor phase Al precursor. At least one of the vapor phase Ti or Ta precursor and the vapor phase Al precursor may contact the substrate in the presence of a vapor phase nitrogen precursor.

Abstract: In various aspects, an organic optoelectronic component and method for producing an organic optoelectronic component are described. An organic optoelectronic component may include a first electrode, an organic functional layer structure above the first electrode, a second electrode above the organic functional layer structure, an adhesive layer structure, and a protective film. The adhesive layer structure may contain a first adhesive layer above the first adhesive layer, and a second adhesive layer above the first adhesive layer. The first adhesive layer may be cured. The second adhesive layer may be adherent and elastic. The protective film may be above the second adhesive layer. The protective film may contain at least one region that is at least partly separated in a lateral direction.

Abstract: A semiconductor memory device includes a substrate, a controller, a semiconductor memory component, first and second capacitors, and a jumper element. The substrate has a conductor pattern. The conductor pattern includes a first conductor portion and a second conductor portion. The first conductor portion overlaps at least a part of the first capacitor in a thickness direction of the substrate and is electrically connected to the first capacitor. The second conductor portion overlaps at least a part of the second capacitor in the thickness direction of the substrate and is electrically connected to the second capacitor. The first conductor portion and the second conductor portion are separated from each other, and are electrically connected to each other by the jumper element.

Abstract: This disclosure relates to image sensors and electronic apparatuses including the same. An image sensor including: a pixel area including shared pixels, wherein each of the shared pixels includes at least two photodiodes that form a group and share a floating diffusion (FD) area; and a transistor (TR) area adjacent to the pixel area, wherein the TR area includes transistor sets corresponding to the shared pixels, wherein, when a first shared pixel and a second shared pixel are arranged adjacent to each other in a first direction, a first TR set corresponding to the first shared pixel and a second TR set corresponding to the second shared pixel share a source region of a first selection TR.

Abstract: A process for producing a light emitting diode device, the process including: forming a plurality of quantum dots on a surface of a layer including a first area and a second area, the forming including: exposing the first area of the surface to light having a first wavelength while exposing the first area to a quantum dot forming environment that causes the quantum dots in the first area to form at a first growth rate while the quantum dots have a dimension less than a first threshold dimension; exposing the second area of the surface to light having a second wavelength while exposing the second area to the quantum dot forming environment that causes the quantum dots in the second area to form at a third growth rate while the quantum dots have a dimension less than a second threshold dimension; and processing the layer to form the LED device.

Abstract: Embodiments of the present invention are directed to a method that incorporates a germanium pull-out process to form semiconductor structures having stacked silicon nanotubes. In a non-limiting embodiment of the invention, a sacrificial layer is formed over a substrate. The sacrificial layer includes a first type of semiconductor material. A pull-out layer is formed on the sacrificial layer. The first type of semiconductor material from the sacrificial layer is removed to form a silicon-rich layer on a surface of the sacrificial layer. The sacrificial layer can be removed such that the silicon-rich layer defines a silicon nanotube.

Abstract: A display device includes a first electrode, a second electrode adjacent to the first electrode, a barrier wall between the first electrode and the second electrode; a wiring arranged above the barrier wall, and arranged between the first electrode and the second electrode, an organic layer covering the first electrode, the second electrode, the barrier wall and the wiring, and a third electrode covering the organic layer, wherein a width of the wiring is narrower than a length between the first electrode and the second electrode, and a resistance value between the wiring and the third electrode is higher than a resistance value between the first electrode and the third electrode.

Abstract: A semiconductor arrangement includes a semiconductor body with a first surface, an inner region and an edge region, the edge region surrounding the inner region, an attachment layer spaced apart from the first surface of the semiconductor body in a first direction, an intermediate layer arranged between the first surface of the semiconductor body and the attachment layer, and at least one first type sealing structure. The sealing structure includes a first barrier, a second barrier, and a third barrier. The first barrier is arranged in the intermediate layer and spaced apart from the attachment layer in the first direction. The second barrier is arranged in the intermediate layer, is spaced apart from the first surface in the first direction, and is spaced apart from the first barrier in a second direction. The third barrier extends from the first barrier to the second barrier in the second direction.

Abstract: A building automation system (BAS) includes building equipment located within a building and a BAS network configured to facilitate communications between the building equipment. The building equipment operate to affect a variable state or condition within the building. The BAS includes a BAS-BIM integrator configured to receive BAS points from the BAS network and to integrate the BAS points with a building information model (BIM). The BIM includes a plurality of BIM objects representing the building equipment. The BAS includes an integrated BAS-BIM viewer configured to use the BIM with the integrated BAS points to generate a user interface. The user interface includes a graphical representation of the BIM objects and the BAS points integrated therewith.

Abstract: A planar light source emits planar light by power supplied from a mounting member. The planar light source includes an engaging part, a planar-light-emitting panel having a light-emitting surface, and a connecting unit disposed between the engaging part and the planar-light-emitting panel. The engaging part forms a portion of a power supply path for supplying power from the mounting member to the planar-light-emitting panel. The planar-light-emitting panel includes a planar-light-emitting tile and a translucent plate, where one main surface of the planar-light-emitting tile includes a light-emitting region. The planar-light-emitting panel emits, in a lighting state, the planar light from the light-emitting region of the planar-light-emitting tile through the translucent plate. An output of the planar light from the planar light source is adjusted by pressing the light-emitting surface.

Abstract: A semiconductor device and a method of making the same. The device includes an electrically conductive heat sink having a first surface. The device also includes a semiconductor substrate. The device further includes a first contact located on a first surface of the substrate. The device also includes a second contact located on a second surface of the substrate. The first surface of the substrate is mounted on the first surface of the heat sink for electrical and thermal conduction between the heat sink and the substrate via the first contact. The second surface of the substrate is mountable on a surface of a carrier.

Abstract: There is provided a ruthenium wiring, including: a TiON film formed as a base film in a recess formed in a predetermined film on a surface of a substrate; and a ruthenium film formed on the TiON film so as to fill the recess.

Abstract: Tunneling field-effect transistors (TFETs) and associated methods of fabrication are disclosed herein. An exemplary TFET includes a protrusion that extends vertically from a substrate. A drain region is in a bottommost portion of the protrusion. A source region is in a topmost portion of the protrusion. A gate stack that wraps a middle portion of the protrusion. The gate stack further wraps around a portion of the source region and a portion of the drain region. Spacers are along a portion of the topmost portion of the protrusion. The TFET further includes a drain contact coupled to the drain region, a gate contact coupled to the gate stack, and a source contact coupled to the source region. The source contact has a width that is greater than a width of the source region. The source contact is disposed on the source region and a portion of the spacers.

Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure formed over a substrate and a gate structure formed across the fin structure. In addition, the gate structure includes a gate dielectric layer formed over the substrate and a work function metal layer formed over a portion of the gate dielectric layer. The gate structure further includes a gate electrode layer formed over a portion of the work function metal layer. In addition, a top surface of the gate electrode layer is located at a position that is higher than that of a top surface of the gate dielectric layer, and the top surface of the gate dielectric layer is located at a position that is higher than that of a top surface of the work function layer.

Abstract: An integrated circuit architecture that provides a path having relatively low thermal resistance between one or more electronic devices and one or more thermal structures formed on an insulator layer on a substrate. Independent parallel thermal conduction paths are provided through the insulator layer, such as a buried oxide (“BOX”) layer, to allow heat to flow from the substrate layer to a collector column having a portion in common with a thermal structure disposed upon the BOX layer. In some cases, the substrate is a silicon substrate layer supporting the thermal structure and the collector column and a heat source, such as an electronic device (e.g., power amplifier, transistor, diode, resistor, etc.).

Abstract: The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region.

Abstract: A finFET device having a substrate and a fin disposed on the substrate. The fin includes a passive region, a stem region overlying the passive region, and an active region overlying the stem region. The stem region has a first width and the active region has a second width. The first width is less than the second width. The stem region and the active region also have different compositions. A gate structure is disposed on the active region.

Abstract: The disclosed embodiments include a method, apparatus, and computer program product for generating hybrid computational meshes around complex and discrete fractures for the purpose of reservoir simulation. For example, one disclosed embodiment includes a method that comprises receiving a set of 3D fracture surfaces with geometry that has been discretized in a 2D manifold by a collection of polygons. The method defines a family of non-intersecting 2D slicing surfaces for slicing the set of 3D fracture surfaces. The method then uses the intersection of the 2D slicing surface with the 2D manifolds defining the fracture surfaces to create a set of 2D fractures on each slicing surface. Following a series of steps, the method generates three-dimensional shells connecting a set of stadia corresponding to each fracture on each 2D slicing surface to a corresponding set of stadia on a neighboring 2D slicing surface for creating a three-dimensional model.

Abstract: A method for fabricating a high-voltage insulated gate type bipolar semiconductor device by comparing to a reference structure of the same includes determining a width S of a mesa region in which the gate insulating film and the MOS transistor are formed, and a trench depth DT, based on a scaling ratio K, in comparison with a second width and a second trench depth of the reference structure, and setting a cell width 2W of the high-voltage insulated gate type bipolar semiconductor device to be equal in length to a second length of the reference structure, the scaling ratio K being defined as K=Y/X, where X indicates a size of a target portion to be miniaturized in the high-voltage insulated gate type bipolar semiconductor device, and Y indicates a size of a target portion to be miniaturized in the reference structure.