Abstract: A semiconductor structure including a first metal line and a second metal line in a dielectric layer, the first metal line and the second metal line are adjacent and within the same dielectric level; an air gap structure in the dielectric layer and between the first metal line and the second metal line, wherein the air gap structure includes an air gap oxide layer and an air gap; and a barrier layer between the air gap structure and the first metal line, wherein the barrier layer is an oxidized metal layer.

Abstract: Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material.

Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a first package body and at least one connecting element. The substrate has a first surface. The first package body is disposed adjacent to the first surface of the substrate, and defines at least one cavity. The connecting element is disposed adjacent to the first surface of the substrate and in a corresponding cavity. A space is defined between a periphery surface of a portion of the connecting element and a sidewall of a portion of the cavity. An end portion of the connecting element extends beyond an outermost surface of the first package body.

Abstract: A FET employing a micro-scale device array structure comprises a substrate on which an epitaxial active channel area has been grown, with a plurality of micro-cells uniformly distributed over the active channel area. Each micro-cell comprises a source electrode, a drain electrode, and at least one gate electrode, with a first metal layer interconnecting either the drain or the source electrodes, a second metal layer interconnecting the gate electrodes, and a third metal layer interconnecting the other of the drain or source electrodes. Each micro-cell preferably comprises a source or drain electrode at the center of the micro-cell, with the corresponding drain or source electrode surrounding the center electrode. The number and width of the gate electrodes in each micro-cell may be selected to achieve a desired power density and/or heat distribution, and/or to minimize the FET's junction temperature. The FET structure may be used to form, for example, HEMTs or MESFETs.

Abstract: A transparent conductive film includes a substrate having opposed first and second surfaces; a first hard coating layer formed on the first surface; a first optical adjustment layer formed on the first hard coating layer, the first optical adjustment layer comprising a second binder resin and a plurality of second particles distributed in the second binder resin; a first transparent conductor layer formed on the first optical adjustment layer, the first transparent conductor layer having a plurality of protrusions on a surface thereof corresponding to the plurality of second particles; a second hard coating layer formed on the second surface; a second optical adjustment layer formed on the second hard coating layer; and a second transparent conductor layer formed on the second optical adjustment layer.

Abstract: A method for forming a tunneling field-effect transistor (TFET) is disclosed. The method includes etching a semiconductor substrate to form a semiconductor protrusion that protrudes out from a top surface of the semiconductor substrate, forming a drain region in lower portion of the semiconductor protrusion, and patterning a gate stack layer to form a gate stack. The gate stack has a gating surface that directly contacts and wraps around a middle portion of the semiconductor protrusion. The method further includes forming a source region in an upper portion of the semiconductor protrusion and forming a source contact over the source region, the source contact have a first width that is larger than a width of the source region.