Abstract: A composite-substrate manufacturing method is provided with: a step of carrying out implantation of ions through a surface of a bulk substrate composed of the nitride compound semiconductor; a step of setting said surface of the bulk substrate against the second substrate, and bonding the bulk substrate and the second substrate together to obtain a bonded substrate; a step of elevating the temperature of the bonded substrate to a first temperature; a step of sustaining the first temperature for a fixed time; and a step of producing a composite substrate by severing the remaining portion of the bulk substrate from the bonded substrate; characterized in that a predetermined formula as for the first temperature, the thermal expansion coefficient of the first substrate, and the thermal expansion coefficient of the second substrate is satisfied.

Abstract: A method for etching an insulating film includes the steps of forming an insulating film; forming a first resin layer composed of a non-silicon-containing resin on the insulating film; forming a pattern including projections and recesses in the first resin layer; forming a second resin layer composed of a silicon-containing resin to cover the projections and the recesses of the pattern in the first resin layer; etching the second resin layer by reactive ion etching with etching gas containing CF4 gas and oxygen gas until the projections of the first resin layer are exposed, a Si component of the second resin layer being oxidized in etching the second resin layer; selectively etching the first resin layer until the insulating film is exposed using as a mask the second resin layer buried in the recesses of the first resin layer to form a resin layer mask; and etching the insulating film using the resin layer mask.

Abstract: A method includes the step of preparing a GaN-based substrate 10, the step of forming on the substrate a nitride-based semiconductor multilayer structure including a p-type AldGaeN layer (p-type semiconductor region) 26, the p-type AldGaeN layer 26 being made of an AlxInyGazN semiconductor (x+y+z=1, x?0, y?0, z?0), and a principal surface of the p-type AldGaeN layer 26 being an m-plane, the step of forming a metal layer 28 which contains at least one of Mg and Zn on the principal surface of the p-type AldGaeN layer 26 and performing a heat treatment, the step of removing the metal layer 28, and the step of forming a p-type electrode on the principal surface of the p-type AldGaeN layer 26, wherein the heat treatment causes a N concentration to be higher than a Ga concentration in the p-type AldGaeN layer 26.

Abstract: The present invention provides a method of forming an opening on a semiconductor substrate. First, a substrate is provided. Then a dielectric layer and a cap layer are formed on the substrate. A ratio of a thickness of the dielectric layer and a thickness of the cap layer is substantially between 15 and 1.5. Next, a patterned boron nitride layer is formed on the cap layer. Lastly, an etching process is performed by using the patterned hard mask as a mask to etch the cap layer and the dielectric layer so as to form an opening in the cap layer and the dielectric layer.

Abstract: A method is demonstrated to form an SOI substrate having a silicon layer with reduced surface roughness in a high yield. The method includes the step of bonding a base substrate such as a glass substrate and a bond substrate such as a single crystal semiconductor substrate to each other, where a region in which bonding of the base substrate with the bond substrate cannot be performed is provided at the interface therebetween. Specifically, the method is exemplified by the combination of: irradiating the bond substrate with accelerated ions; forming an insulating layer over the bond substrate; forming a region in which bonding cannot be performed in part of the surface of the bond substrate; bonding the bond substrate and the base substrate to each other with the insulating layer therebetween; and separating the bond substrate from the base substrate, leaving a semiconductor layer over the base substrate.

Abstract: A method of preparing a silicon nanowire and a method of fabricating a lithium secondary battery including the silicon nanowire are provided. The method of preparing a silicon nanowire may include forming a catalyst layer including metal particles separated from one another on a silicon layer, selectively etching the silicon layer contacting the metal particles, and removing the metal particles.

Abstract: A method for fabricating a thin film photovoltaic device. The method includes providing a substrate comprising an absorber layer and an overlying window layer. The substrate is loaded into a chamber and subjected to a vacuum environment. The vacuum environment is at a pressure ranging from 0.1 Torr to about 0.02 Torr. In a specific embodiment, a mixture of reactant species derived from diethylzinc species, water species and a carrier gas is introduced into the chamber. The method further introduces a diborane species using a selected flow rate into the mixture of reactant species. A zinc oxide film is formed overlying the window layer to define a transparent conductive oxide using the selected flow rate to provide a resistivity of about 2.5 milliohm-cm and less and an average grain size of about 3000 to 5000 Angstroms.

Abstract: An apparatus and method to inspect a defect of a substrate. Since a recess of an under layer of a substrate is darker than a projection of a top layer, a ratio of a value of a secondary electron signal (of an SEM) of the under layer to a value of the top layer may be increased to improve a pattern image used to inspect an under layer defect. Several conditions under which electron beams are irradiated may be set, and the pattern may be scanned under such conditions. Secondary electron signals may be generated according to the conditions and converted into image data to display various pattern images. Scan information on the images may be stored with positional information on the substrate. Each of scan information on the pattern images may be calculated to generate a new integrated image.

Abstract: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.

Abstract: A method of fabricating a non-volatile memory device is provided. The method includes sequentially forming a tunnel insulation layer and a first polysilicon layer on a substrate, patterning the first polysilicon layer and the tunnel insulation layer, forming a dielectric layer to cover the patterned first polysilicon layer and the patterned tunnel insulation layer, forming a gate insulation layer on the substrate where the substrate is exposed, forming a second polysilicon layer to cover the dielectric layer, and forming a first floating gate and a second floating gate a fixed distance apart from each other, the forming of the first and second floating gates including etching middle portions of the second polysilicon layer, the dielectric layer, the patterned first polysilicon layer, and the patterned tunnel insulation layer, and separating the etched layers into two parts.

Abstract: The present invention improves the performance of a semiconductor device wherein a metal silicide layer is formed through a salicide process. A metal silicide layer is formed over the surfaces of first and second gate electrodes, n+-type semiconductor regions, and p+-type semiconductor regions through a salicide process of a partial reaction type without the use of a salicide process of a whole reaction type. In a heat treatment for forming the metal silicide layer, by heat-treating a semiconductor wafer not with an annealing apparatus using lamps or lasers but with a thermal conductive annealing apparatus using carbon heaters, a thin metal silicide layer is formed with a small thermal budget and a high degree of accuracy and microcrystals of NiSi are formed in the metal silicide layer through a first heat treatment.

Abstract: According to one embodiment, a semiconductor device manufacturing method includes producing a first substrate with an electrode, producing a second substrate with a through hole, stacking the second substrate on the first substrate, with an insulating layer intervening between the first substrate and the second substrate, making a hole reaching the electrode in the insulating layer under the through hole by etching the insulating layer with the second substrate as a mask, and filling the through hole and the hole with conductive substance.

Abstract: The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer.

Abstract: A method of forming a polymer device including the steps (i) of depositing on a substrate a solution containing a polymer or oligomer and a crosslinking moiety, to form a layer, and, (ii) curing the layer formed in step (i) under conditions to form an insoluble crosslinked polymer, wherein the crosslinking moiety is present in step (i) in an amount in the range of from 0.05 mol % to 5 mol % based on the total number of moles or repeat units of the polymer or oligomer and the crosslinking moiety in the solution.

Abstract: This method for producing a non-plane comprises fitting a flexible component onto a carrier by means of hybridization columns, each column having a first height and including a volume of solder material formed between two surfaces wettable by said solder material added to the flexible component and to the carrier respectively, said wettable surfaces being surrounded by zones non-wettable by the solder material, the wettable surfaces and the volume of solder material being determined as a function of a second height required for the flexible component relative to the carrier at the place where the column is formed, such that the column varies from the first height to the second height when the volume of material is brought to a temperature higher than or equal to its melting point and heating the volumes of solder material of the columns to a temperature higher than or equal to the melting point of said material in order to melt it.

Abstract: A structure and method for replacement metal gate technology is provided for use in conjunction with semiconductor fins or other devices. An opening is formed in a dielectric by removing a sacrificial gate material such as polysilicon. The surfaces of the semiconductor fin within which a transistor channel is formed, are exposed in the opening. A replacement metal gate is formed by forming a diffusion barrier layer within the opening and over a gate dielectric material, the diffusion barrier layer formation advantageously followed by an in-situ plasma treatment operation. The treatment operation utilizes at least one of argon and hydrogen and cures surface defects in the diffusion barrier layer enabling the diffusion barrier layer to be formed to a lesser thickness. The treatment operation decreases resistivity, densifies and alters the atomic ratio of the diffusion barrier layer, and is followed by metal deposition.

Abstract: A sample with at least a first structure and a second structure is measured and a first model and a second model of the sample are generated. The first model models the first structure as an independent variable and models the second structure. The second model of the sample models the second structure as an independent variable. The measurement, the first model and the second model together to determine at least one desired parameter of the sample. For example, the first structure may be on a first layer and the second structure may be on a second layer that is under the first layer, and the processing of the sample may at least partially remove the first layer, wherein the second model models the first layer as having a thickness of zero.

Abstract: The present invention relates to a method for processing semiconductor devices with a fine structure, and more particularly, to a processing method suitable for miniaturizing semiconductor devices with a so-called high-k/metal gate structure. In an embodiment of the present invention, a deposited film, which includes an insulating film made of Hf or Zr and a material of Mg, Y or Al existing on, under or in the insulating film, is formed on a Si substrate and is removed by repeating a dry etching process and a wet etching process at least one time. The wet etching process is performed prior to the dry etching process.

Abstract: Disclosed herein is a thin film prepared using a mixture of nanocrystal particles and a molecular precursor. The nanocrystal is used in the thin film as a nucleus for crystal growth to minimize grain boundaries of the thin film and the molecular precursor is used to form the same crystal structure as the nanocrystal particles, thereby improving the crystallinity of the thin film. The thin film can be used effectively in a variety of electronic devices, including thin film transistors, electroluminescence devices, memory devices, and solar cells. Further disclosed is a method for preparing the thin film.

Abstract: Manufacturing a laser diode includes growing an active layer, a first InP layer, and a diffraction grating layer; forming an alignment mark having a recess by etching the diffraction grating layer and the first InP layer; forming a first etching mask; forming a diffraction grating in the diffraction grating layer using the first etching mask; forming a modified layer containing InAsP on a surface of the alignment mark recess by supplying a first source gas containing As and a second source gas containing P; growing a second InP layer on the diffraction grating layer and on the alignment mark; forming a second etching mask on the second InP layer; selectively etching the second InP layer embedded in the recess of the alignment mark through the second etching mask by using the modified layer serving as an etching stopper; and forming a waveguide structure using the alignment mark.