Abstract: A semiconductor device and a method for forming a device are presented. A wafer substrate having first and second regions is provided. The second region includes an inner region of the substrate while the first region includes an outer peripheral region from an edge of the substrate towards the inner region. A protection unit is provided above the substrate. The protection unit includes a region having a total width WT defined by outer and inner rings of the protection unit. The substrate is etched to form at least a trench in the second region of the substrate. The WT of the protection unit is sufficiently wide to protect the first region of the wafer substrate such that the first region is devoid of trench.

Abstract: In a method of manufacturing a semiconductor device, a body region is formed in an epitaxial layer provided on a semiconductor substrate. A part of a semiconductor material forming the body region surface is removed to form a convex-type contact region protruding from the body region surface and to form a shallow trench surrounding the convex-type contact region. A deep trench region is formed so as to extend from the shallow trench surface to inside of the epitaxial layer. A gate insulating film is formed on an inner wall of the deep trench region which is filled with polycrystalline silicon that is held in contact with the gate insulating film. A source region and a body contact region are formed in the shallow trench and the convex-type contact region, respectively, and a silicide layer is formed to connect the source region and the body contact region to each other.

Abstract: Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.

Abstract: The invention relates to a method for fabricating a structure including a semiconductor material comprising: a) implanting one or more ion species to form a weakened region delimiting at least one seed layer in a substrate of semiconductor material, b) forming, before or after step a), at least one metallic layer on the substrate in semiconductor material, c) assembling the at least one metallic layer with a transfer substrate, then fracturing the implanted substrate at the weakened region, and d) forming at least one layer in semiconductor material on the at least one seed layer, for example, by epitaxy.

Abstract: The invention relates to an organic electronic device, particularly an OLED device (100), and to a method for its manufacturing. The device (100) comprises at least one functional unit (LU1, LU2, LU3) with an organic layer (120). On top of this functional unit (LU1, LU2, LU3), at least one inorganic encapsulation layer (140, 141) and at least one organic encapsulation layer (150, 151) are disposed in which at least one conductive line (161, 162) is embedded. In this way an OLED with a thin film encapsulation can be provided that can electrically be contacted at contact points (CL) on its back side.

Abstract: The method of manufacturing a semiconductor device in accordance with the present invention provides a metal-containing film capable of adjusting a work function. The including: (a) alternately supplying a first source containing a first metal element and a halogen element and a second source containing a second metal element different from the first metal element and at least one selected from the group consisting of a ligand of a methyl group, a ligand of an ethyl group and a ligand of a cyclopenta-based group onto a substrate in a process chamber to form a composite metal-containing film on the substrate; and (b) alternately supplying a third source containing a third metal element and a fourth source containing nitrogen onto the substrate in the process chamber to form a metal nitride film on the composite metal-containing film.

Abstract: A method for reducing the tilt of an optical unit during manufacture of an image sensor includes the steps of: providing a semimanufacture of the image sensor, carrying out a preheating process, carrying out an adhesive application process, carrying out an optical unit mounting process, and carrying out a packaging process. Due to the preheating process, the semimanufacture will be subjected to a stabilized process environment during the adhesive application process and the optical unit mounting process, so as for the optical unit to remain highly flat once attached to the semimanufacture. The method reduces the chances of tilt and crack of the optical unit and thereby contributes to a high yield rate.

Abstract: A MOS transistor includes a pair of impurity regions formed in a substrate as spaced apart from each other, and a gate electrode formed on a region of the substrate located between the pair of impurity regions. Each of the impurity regions is formed of a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The first epitaxial layer is formed of at least one first sub-epitaxial layer and a respective second sub-epitaxial layer stacked on each first sub-epitaxial layer. An impurity concentration of the first sub-epitaxial layer is less than that of the second sub-epitaxial layer.

Abstract: According to one embodiment, a pattern formation method includes: forming a block copolymer layer containing a polystyrene derivative and an acrylic having 6 or more carbon atoms on a side chain in an opening of a resist layer provided on an underlayer and having the opening; forming a first layer containing the polystyrene derivative and a second layer containing the acrylic in the opening by phase-separating the block copolymer layer; and removing the second layer.

Abstract: A chemical vapor deposition apparatus includes: a reaction chamber including an inner tube having a predetermined volume of an inner space, and an outer tube tightly sealing the inner tube; a wafer holder disposed within the inner tube and on which a plurality of wafers are stacked at predetermined intervals; and a gas supply unit including at least one gas line supplying an external reaction gas to the reaction chamber, and a plurality of spray nozzles communicating with the gas line to spray the reaction gas to the wafers, whereby semiconductor epitaxial thin films are grown on the surfaces of the wafers, wherein the semiconductor epitaxial thin film grown on the surface of the wafer includes a light emitting structure in which a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer are sequentially formed.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate having a mask layer formed thereon, providing a first photomask having a first layout pattern and a second photomask having a second layout pattern, the first layout pattern including a plurality of active area portions and at least a neck portion connecting two adjacent active area portions, transferring the first layout pattern from the first photomask to the mask layer to form a plurality of active area patterns and at least a neck pattern connecting two adjacent active area patterns in the mask layer, and transferring the second layout pattern from the second photomask to the mask layer to remove the neck pattern to form a patterned mask. The patterned mask includes the active area patterns. A slot is at least formed between the two adjacent active area patterns.

Abstract: A substrate processing apparatus includes a process chamber which processes a substrate, a conductive substrate support table which is installed within the process chamber, a dielectric plate on which the substrate is mounted, the dielectric plate being placed on the substrate support table, a microwave generator which is installed outside the process chamber, and a microwave supplying unit which supplies a microwave generated by the microwave generator into the process chamber.

Abstract: The methods and apparatus disclosed herein concern a process that may be referred to as a “soft anneal.” A soft anneal provides various benefits. Fundamentally, it reduces the internal stress in one or more silicon layers of a work piece. Typically, though not necessarily, the internal stress is a compressive stress. A particularly beneficial application of a soft anneal is in reduction of internal stress in a stack containing two or more layers of silicon. Often, the internal stress of a layer or group of layers in a stack is manifest as wafer bow. The soft anneal process can be used to reduce compressive bow in stacks containing silicon. The soft anneal process may be performed without causing the silicon in the stack to become activated.

Abstract: A system for separating semiconductor devices from a wafer having back metal exposed in scribe streets of the wafer positioned on a plastic film by applying a variable radial force to stretch and tension the film while controlling the stretch and tension as a function of a control parameter.

Abstract: Generally, the subject matter disclosed herein relates to various methods of making a capacitor with a sealing liner and a semiconductor device including such a capacitor. In one example, the method includes forming a layer of insulating material, forming a capacitor opening in the layer of insulating material, forming a sealing liner on the sidewalls of the capacitor opening and forming a first metal layer in the capacitor opening and on the sealing liner by performing a process using a precursor having a minimum particle size, wherein the sealing liner is made of a material having an opening size that is less than the minimum particle size of the precursor.

Abstract: Methods of fabricating semiconductor devices include forming a metal silicide in a portion of a crystalline silicon layer, and etching the metal silicide using an etchant selective to the metal silicide relative to the crystalline silicon to provide a thin crystalline silicon layer. Silicon-on-insulator (SOI) substrates may be formed by providing a layer of crystalline silicon over a base substrate with a dielectric material between the layer of crystalline silicon and the base substrate, and thinning the layer of crystalline silicon by forming a metal silicide layer in a portion of the crystalline silicon, and then etching the metal silicide layer using an etchant selective to the metal silicide layer relative to the crystalline silicon.

Abstract: A method of assembling a matrix of photovoltaic cells includes positioning photovoltaic cells in a desired orientation, aligning the row of photovoltaic cells relative to each other, and enabling a homogeneous downward pressure on the row of photovoltaic cells to facilitate electrical and mechanical connectivity between the photovoltaic cells.

Abstract: An organic electroluminescent element having a structure in which a plurality of light-emitting layers stacked between a first electrode with light reflectivity and a second electrode with optical transparency while one or more interlayers with a light transmissive property are interposed between the plurality of light-emitting layers. A first interlayer is formed as the interlayer closest to the first electrode. A first light-emitting unit is formed between the first electrode and the first interlayer to include a first light-emitting layer which has a first light-emitting source, and a second light-emitting unit is formed on a side of the first interlayer close to the second electrode to include a second light-emitting layer which has a second light-emitting source. The first interlayer is a semi-transmissive layer which has both of optical transparency and light reflectivity and has a total light absorption ratio of 10% or less.

Abstract: A method of removing a hard mask used for patterning gate stacks including patterning gate stacks on a substrate, wherein the hard mask is deposited over the gate stacks. The method further includes depositing a dielectric layer on the substrate after the gate stacks are patterned and planarizing a first portion of the dielectric layer. The method further includes removing a second portion of the dielectric layer and the hard mask by using an etching gas and etching the remaining dielectric layer by using a wet etching chemistry.

Abstract: A method for manufacturing an image sensor, including the steps of: forming elementary structures of an image sensor on the first surface of a semiconductor substrate; installing a layer on the first surface; defining trenches in the layer, the trenches forming a pattern in the layer; and installing, on a hollow curved substrate, the obtained device on the free surface side of the layer, the pattern being selected according to the shape of the support surface.