Abstract: An opto-electronic device includes: (1) a substrate including a first region and a second region; and (2) a conductive coating covering the second region of the substrate. The first region of the substrate is exposed from the conductive coating, and an edge the conductive coating adjacent to the first region of the substrate has a contact angle that is greater than about 20 degrees.

Abstract: A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles, a first plurality of leads, and a second plurality of leads. A respective end surface of each lead of the first plurality of leads and the second plurality of leads is plated with a metal. A first respective window on a first side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A second respective window on a second side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A method for fabricating a semiconductor package comprises the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, and applying a cutting process or a punching process.

Abstract: An electronic package can include a substrate, a first die and a second die. The first die can include a first thickness and the second die can include a second thickness. The first and second dies can be coupled to the substrate. A mold can be disposed on the substrate and cover the first die and the second die. The mold can include a planar upper surface. A first via, having a first length, can be extended between the first die and the planar upper surface. A second via, having a second length, can be extended between the second die and the planar upper surface. In some examples, a third die can be communicatively coupled to the first die using the first via and the second die using the second via.

Abstract: A printed circuit board (PCB) system includes a first printed circuit board (PCB), an integrated circuit (IC) package, and a memory module. The IC package includes i) a package substrate, ii) a main IC chip that is electrically coupled to a top surface of the package substrate, iii) first contact structures that are disposed on a bottom surface of the package substrate and that are electrically coupled to the first PCB, and iv) second contact structures that are disposed on a top surface of the package substrate. The memory module includes i) a second PCB, ii) one or more memory IC chips that are disposed on the second PCB, and iii) third contact structures that are disposed on a bottom surface of the second PCB. An interposer electrically couples the second contact structures of the IC package with the third contact structures of the memory module.

Abstract: A semiconductor device package is disclosed. The package according to one example includes a base having a main surface made of a metal, a dielectric side wall having a bottom surface facing the main surface, a joining material containing silver (Ag) and joining the main surface of the base and the bottom surface of the side wall to each other, a lead made of a metal joined to an upper surface of the side wall on a side opposite to the bottom surface, and a conductive layer not containing silver (Ag). The conductive layer is provided between the bottom surface and the upper surface of the side wall at a position overlapping the lead when viewed from a normal direction of the main surface. The conductive layer is electrically connected to the joining material, extends along the bottom surface, and is exposed from a lateral surface of the side wall.

Abstract: A display device is disclosed, which includes: a substrate; a first metal layer, disposed on the substrate and having a first pinhole; a pixel electrode layer, disposed on the substrate; and a light detecting element for detecting a light passing through the first pinhole, wherein the first metal layer is disposed between the substrate and the pixel electrode layer.

Abstract: A mounting structure for a heater element includes a heater element having a surface to be cooled, a board on which the heater element is mounted, a cooling member that cools the surface to be cooled of the heater element mounted on the board, and a supporting member temporarily fixed to the board, the supporting member temporarily fixing the heater element.

Abstract: In this semiconductor device, a positioning protrusion is formed at a side surface of a sealing resin from which one end of a main electrode wire protrudes. Thus, the outer size of the sealing resin can be reduced as compared to a case where a positioning protrusion is formed at the bottom of the sealing resin. In addition, a thickness regulating protrusion is provided with a space from solder. Thus, it is possible to prevent interface separation or crack that would occur starting from a contact part between the thickness regulating protrusion and the solder, whereby the life of a joining part between a semiconductor module and a cooler can be ensured. Accordingly, a semiconductor device having enhanced heat dissipation property and reliability is obtained without increase in the outer size of the semiconductor module.

Abstract: This semiconductor device is provided with a device substrate in which a semiconductor circuit including two high frequency amplifiers; a cap substrate and a sealing frame of a conductor which forms and air-tightly seals space surrounding an area, in which the semiconductor circuit is formed, between the device substrate and the cap substrate, wherein the sealing frame is configured as a line of a 90-degree hybrid circuit or a line of a rat-race circuit.

Abstract: A semiconductor package includes a first semiconductor chip mounted on the package substrate, a second semiconductor mounted on the package substrate and set apart from the first semiconductor chip in a horizontal direction thereby forming a gap between the first semiconductor chip and the second semiconductor chip. The semiconductor package further includes a first thermal interface material layer formed in the gap and having a first modulus of elasticity and a second thermal interface material layer formed on each of the first semiconductor chip and the second semiconductor chip and having a second modulus of elasticity, wherein the first modulus of elasticity is less than the second modulus of elasticity.

Abstract: An electronic device includes a package structure, a first lead and a second lead. The first lead has a first portion extending outward from a side of the package structure and downward, and a second portion extending outward from the first portion away from the package side. The second lead has a first portion extending outward from the package side and downward, and a second portion extending inward from the first portion toward the package side, and a distal end of the second lead is spaced from the package side.

Abstract: In one example, an electronic device comprises a base substrate comprising a base substrate conductive structure, a first electronic component over a first side of the base substrate, an encapsulant over the first side of the base substrate, wherein the encapsulant contacts a lateral side of the electronic component, an interposer substrate over a first side of the encapsulant and comprising an interposer substrate conductive structure, and a vertical interconnect in the encapsulant and coupled with the base substrate conductive structure and the interposer substrate conductive structure. A first one of the base substrate or the interposer substrate comprises a redistribution layer (RDL) substrate, and a second one of the base substrate or the interposer substrate comprises a laminate substrate. Other examples and related methods are also disclosed herein.

Abstract: An integrated circuit includes a resistive material layer formed on a substrate, a metal layer formed on the resistive material layer, a bipolar transistor formed on the substrate, and a resistive element formed on the substrate. The bipolar transistor includes, as a sub-layer, the metal layer formed in a first region, and also includes a collector layer formed on the sub-collector layer. The resistive element is constituted by the resistive material layer formed in a second region.

Abstract: According to the present invention, a power module that has a base to which a power semiconductor device is bonded and a sealing body for sealing said base and in which the base and the sealing body are bonded with a primer layer interposed therebetween, said primer layer being formed of a cured product of a silicone-modified polyimide resin composition containing, for example, components (A) to (E) below, has high reliability because delamination of an epoxy sealing resin under high temperature conditions is suppressed. (A) Silicone-modified polyimide resin represented by formula (1) Ee-Ff-Gg??(1) E is represented by formula (2), F is represented by formula (3), G is a divalent group derived from diamine, f+e+g=100 mol %, the molar ratio f/(e+g) is 0.9-1.1, and e is 1-90 when the sum of e and g is 100.

Abstract: A semiconductor device of an embodiment includes: a wiring board; a semiconductor chip mounted on the wiring board; and a resin-containing layer bonded on the wiring board so as to fix the semiconductor chip to the wiring board. The resin-containing layer contains a resin-containing material having a breaking strength of 15 MPa or more at 125° C.

Abstract: Semiconductor packages and package assemblies having active dies and external die mounts on a silicon wafer, and methods of fabricating such semiconductor packages and package assemblies, are described. In an example, a semiconductor package assembly includes a semiconductor package having an active die attached to a silicon wafer by a first solder bump. A second solder bump is on the silicon wafer laterally outward from the active die to provide a mount for an external die. An epoxy layer may surround the active die and cover the silicon wafer. A hole may extend through the epoxy layer above the second solder bump to expose the second solder bump through the hole. Accordingly, an external memory die can be connected directly to the second solder bump on the silicon wafer through the hole.

Abstract: A contact area structure including an organic substrate, an inorganic conductive layer, an organic adhesive layer, and a transparent conductive layer is provided. The organic substrate includes at least one contact pad area including a first block and a second block adjacent to the first block. The inorganic conductive layer is disposed on the organic substrate, in which the inorganic conductive layer is partially disposed on the first block, and a portion of an upper surface of the organic substrate is exposed at the second block. The inorganic conductive layer and the upper surface of the organic substrate are covered by the organic adhesive layer. The transparent conductive layer is disposed on the organic adhesive layer, so that the adhesive strength between the transparent layer and the inorganic conductive layer can be enhanced.

Abstract: In some examples, an electronic package and methods for forming the electronic package are described. The electronic package can be formed by disposing an interposer on a surface of a substrate having a first pitch wiring density. The interposer can have a second pitch wiring density different from the first pitch wiring density. A layer of non-conductive film can be situated between the interposer and the surface of the substrate. A planarization process can be performed on a surface of the substrate. A solder resist patterning can be performed on the planarized surface the substrate. A solder reflow and coining process can be performed to form a layer of solder bumps on top of the planarized surface of the substrate. The interposer can provide bridge connection between at least two die disposed above the substrate. Solder bumps under the interposer electrically connect the substrate and the interposer.

Abstract: A method of fabricating high electron mobility transistor, including the steps of providing a substrate with active areas, forming a buffer layer, a channel layer and a barrier layer sequentially on the substrate and gate, source and drain on the barrier layer, forming a trench surrounding the channel layer and the barrier layer, and forming a trench isolation structure in the trench, wherein the trench isolation structure applies stress on the channel layer and the barrier layer and modify two-dimension electron gas (2DEG) or two-dimension hole gas (2DHG) of the high electron mobility transistor.

Abstract: It is an object to reduce a difference in temperature of a refrigerant between an upstream side and a downstream side of a flow path even in a case where all semiconductor elements generate heat due to inverter operation and the like. A semiconductor device includes at least one semiconductor element, a base plate, a plurality of cooling fins, a jacket, and a partition. The partition is disposed below the plurality of cooling fins in the jacket. The partition has at least one inflow opening to allow the refrigerant having flowed in through the refrigerant inlet to flow through the plurality of cooling fins, and has a portion abutting the jacket on the side of the refrigerant inlet. The at least one inflow opening is located to correspond to the at least one semiconductor element.