Abstract: A memory device includes a bit line, a source line, a plurality of word lines, and a memory cell. The memory cell includes a plurality of memory strings coupled in parallel between the bit line and the source line. Each of the plurality of memory strings includes a plurality of memory elements coupled in series between the bit line and the source line, and electrically coupled correspondingly to the plurality of word lines.

Abstract: A method and apparatus for accumulating and storing respective access counts of a plurality of word lines in a memory module are provided. The method may include: within a memory bank positioned in the memory module, providing a plurality of extraordinary storage cells coupled to the plurality of word lines; and utilizing the plurality of extraordinary storage cells to accumulate and store the respective access counts of the plurality of word lines, wherein multiple sets of extraordinary storage cells in the plurality of extraordinary storage cells correspond to the plurality of word lines, respectively.

Abstract: In a compute-in-memory (“CIM”) system, current signals, indicative of the result of a multiply-and-accumulate operation, from a CIM memory circuit are computed by comparing them with reference currents, which are generated by a current digital-to-analog converter (“DAC”) circuit. The memory circuit can include non-volatile memory (“NVM”) elements, which can be multi-level or two-level NVM elements. The characteristic sizes of the memory elements can be binary weighted to correspond to the respective place values in a multi-bit weight and/or a multi-bit input signal. Alternatively, NVM elements of equal size can be used to drive transistors of binary weighted sizes. The current comparison operation can be carried out at higher speeds than voltage computation. In some embodiments, simple clock-gated switches are used to produce even currents in the current summing branches. The clock-gated switches also serve to limit the time the cell currents are on, thereby reducing static power consumption.

Abstract: System and methods for implementing a multiply and accumulate (MAC) operation are described. In an example, a device can multiply an input digital signal with an input current to generate a current signal. The device can further divide the current signal into a plurality of currents. The device can further sample the plurality of currents sequentially using the same clock frequency. The device can further combine the plurality of sampled currents to generate an output current signal.

Abstract: A processing-in-memory (PIM) device includes a multiplier circuit, a memory circuit, and an address pipeline circuit. The multiplier circuit is configured to perform an element-wise multiplication (EWM) calculation of first input data and second input data to generate result data. The memory circuit is configured to output the first input data and the second input data to the multiplier circuit in response to a read control signal and is configured to store the result data in response to a write control signal. The address pipeline circuit is configured to receive the read control signal to store an address signal used as a target address signal for designating a region of the memory circuit into which the result data are stored. In addition, the address pipeline circuit is configured to receive the write control signal to output the target address signal to the memory circuit.

Abstract: A memory device includes a command decoder configured to receive a command, a data clock receiving circuit configured to receive a data clock signal, and a control logic configured to control the data clock receiving circuit based on the command decoded by the command decoder, and enable the data clock receiving circuit. The control logic enables the data clock receiving circuit in response to the memory device receiving a dynamic data clock command. The data clock receiving circuit is in an enabled state until a predetermined particular command is received.

Abstract: A dual-port, dual function memory device can be configured to perform operations on data written to the memory device using artificial intelligence (AI) circuitry, such as a neuromorphic array and/or a deep learning accelerator (DLA), of the memory device. The memory device can include a port dedicated for communication between the AI circuitry and a host device and another port dedicated for communication between a memory array of the memory device and a host device. Performing operations, such as image processing operations, using AI circuitry of a memory device can reduce data transfers, reduce resource consumption, and offload workloads from a host device.

Abstract: A memory device and an operation method thereof are provided. The memory device includes an input/output data latch circuit and a bit line sensing amplifier circuit. The input/output data latch circuit is coupled between a main input/output line pair and a local input/output line pair. The local input/output line pair is coupled to a plurality of bit line pairs through the bit line sensing amplifier circuit. The memory device performs a two-stage operation to input or output data of a selected bit line pair among the bit line pairs. The selected bit line pair connects to the local input/output line pair only during one stage operation of the two-stage operation. Further, during the other stage operation of the two-stage operation, the data of the selected bit line pair latched in the input/output data latch circuit is transmitted to the main input/output line pair.

Abstract: A read-only memory (ROM) computing unit utilized in matrix operations of a neural network comprising a unit element including one or more connections, wherein a weight associated with the computing unit is responsive to either a connection or lack of connection internal to the unit cell or between the unit element and a wordline and a bitline utilized to form an array of rows and columns in the ROM computing unit, and one or more passive or active electrical elements located in the unit element, wherein the passive or active electrical elements are configured to adjust the weight associated with the compute unit, wherein the ROM computing unit is configured to receive an input and output a value associated with the matrix operation, wherein the value is responsive to the input and weight.

Abstract: Magnetoelectric or magnetoresistive memory cells include a magnesium containing nonmagnetic metal dust layer located between a free layer and a dielectric capping layer.

Abstract: Magnetoelectric or magnetoresistive memory cells include a magnesium containing nonmagnetic metal dust layer located between a free layer and a dielectric capping layer.

Abstract: A new family of shared clock single-edge triggered flip-flops that reduces a number of internal clock devices from 8 to 6 devices to reduce clock power. The static pass-gate master-slave flip-flop has no performance penalty compared to the flip-flops with 8 clock devices thus enabling significant power reduction. The flip-flop intelligently maintains the same polarity between the master and slave stages which enables the sharing of the master tristate and slave state feedback clock devices without risk of charge sharing across all combinations of clock and data toggling. Because of this, the state of the flip-flop remains undisturbed, and is robust across charge sharing noise. A multi-bit time borrowing internal stitched flip-flop is also described, which enables internal stitching of scan in a high performance time-borrowing flip-flop without incurring increase in layout area.

Abstract: A memory includes an array with rows and columns of memory cells. The rows include a first row and a second row, which may be adjacent. The memory also includes a plurality of logic gates in the array. Each logic gate of the plurality of logic gates includes a first input coupled to a respective memory cell in the first row, a second input coupled to a respective memory cell in the second row, and an output. The first and second inputs may be connected to internal nodes within the respective memory cells without intervening transistors. The memory further includes a plurality of sense lines in the array. The output of each logic gate of the plurality of logic gates is coupled to a sense line of the plurality of sense lines.

Abstract: An apparatus is provided that includes an array including m rows and n columns of nodes. Each column of nodes is coupled to one of n first conductive lines, and each row of nodes is coupled to one of m second conductive lines. Each node of the m rows and n columns of nodes includes a spin orbit torque-based spin torque oscillator circuit configured to oscillate at a corresponding intrinsic frequency. The spin orbit torque-based spin torque oscillator circuits are configured to generate m output signals at the m second conductive lines upon application of n input signals to corresponding n first conductive lines. The n input signals correspond to an n-element input vector, and each input signal includes a corresponding input signal frequency. Each of the m output signals include frequency domain components at the input signal frequencies.

Abstract: A transpose memory unit for a plurality of multi-bit convolutional neural network based computing-in-memory applications includes a memory cell and a transpose cell. The memory cell stores a weight. The transpose cell is connected to the memory cell and receives the weight from the memory cell. The transpose cell includes an input bit line, at least one first input word line, a first output bit line, at least one second input word line and a second output bit line. One of the at least one first input word line and the at least one second input word line transmits at least one multi-bit input value, and the transpose cell is controlled by the second word line to generate a multiply-accumulate output value on one of the first output bit line and the second output bit line according to the at least one multi-bit input value multiplied by the weight.

Abstract: A self-clocking (or self-oscillating) modulator in signal processing, similar to a ?? modulator, with particular application in the design of neural networks based on such modulators is described. A system of multiple self-clocking modulators and supporting structures may be configured to perform a calculation similar to that of an analog computer, such as a neural network, at lower power and smaller size than a digital implementation. Such a system constructed using the present approach does not require a sequential solution, but rather converges on a solution in one step; unlike the typical prior art, it thus requires no clock and operates asynchronously in a manner similar to a conventional analog computer. The self-clocking modulator can function as a neuron in a neural network, receiving a sum-of-products signal and generating an output stream like that of a ?? modulator that represents this sum-of-products, potentially also including an activation function and offset.

Abstract: A neural network circuit having a plurality of analog-to-digital multipliers generates an analog product-sum voltage corresponding to the sum of charge signals of each of the analog-to-digital multipliers.

Abstract: An in-memory computing memory device is disclosed. The memory device comprises an array of memory cells, a plurality of word lines, a plurality of bit lines, (M+1) input circuits, a wordline driver and an evaluation circuitry. The array is divided into (M+1) lanes and each lane comprises P memory cell columns and an input circuit. The input circuit in each lane charges a predefined bit line with a default amount of charge proportional to an input synapse value and then distributes the default amount of charge to the other second bit lines with a predefined ratio based on a constant current. The evaluation circuitry couples a selected number of the bit lines to an accumulate line and convert an average voltage at the accumulate line into a digital value in response to a set of (M+1) input synapse values and the activated word line.

Abstract: Systems and methods relate to arranging atoms into 1D and/or 2D arrays; exciting the atoms into Rydberg states and evolving the array of atoms, for example, using laser manipulation techniques and high-fidelity laser systems described herein; and observing the resulting final state. In addition, refinements can be made, such as providing high fidelity and coherent control of the assembled array of atoms. Exemplary problems can be solved using the systems and methods for arrangement and control of atoms.

Abstract: A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.