Patents Examined by Albert De Cady
  • Patent number: 6992648
    Abstract: A brightness adjusting apparatus of a reflective type liquid crystal display device is applicable to a portable game machine, for example. The portable game machine is provided with a reflective type color liquid crystal display device, and displayed colors of a game character and a background are determined on the basis of color data included in color palettes. When a player inputs an instruction for brightness adjustment, a brightness adjusting screen is displayed in response thereto, and the color data included in each of an OBJ color palette and a BG color palette is converted on the basis of an adjustment value (parameter) corresponding to designated brightness, and then, the brightness of the object and the brightness of the background are individually adjusted.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: January 31, 2006
    Assignee: Nintendo Co., Ltd.
    Inventor: Yoichi Yamada
  • Patent number: 6263465
    Abstract: The present invention is a simple method of error detection and correction that is easy to implement in data transmission. The invention presents a self-correcting error coding method that advantageously eliminates bandwidth and power penalty. In addition, feedback error control and data retransmission are not required for implementing the method of the invention. System and transmission channel resources are conserved as a result.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: July 17, 2001
    Assignee: Lucent Technologies, Inc.
    Inventor: Narayan L. Gehlot
  • Patent number: 6240330
    Abstract: In current manufacturing practices, if a process results in a partial product which is outside its specification, it is either sent back to be reworked, or is scrapped. This results in unacceptable waste. The present invention comprises a method for minimizing this wasted work and materials, by corrective actions by subsequent processes. This approach is general, and is capable of correcting the effects of out-of-specs manufacturing process conditions, including the salvaging of partial product, thereby obviating the need for rework or scrap.
    Type: Grant
    Filed: May 28, 1997
    Date of Patent: May 29, 2001
    Assignee: International Business Machines Corporation
    Inventors: Jerome M. Kurtzberg, Menachem Levanoni
  • Patent number: 6240535
    Abstract: An IC module, such as a Multi-Chip Module (MCM), includes multiple IC dice, each having a test mode enable bond pad, such as an output enable pad. A fuse incorporated into the MCM's substrate connects each die's test mode enable bond pad to one of the MCM's no-connection (N/C) pins, and a resistor incorporated into the substrate connects the test mode enable bond pads to one of the MCM's ground pins. By applying a supply voltage to the test mode enable bond pads through the N/C pin, a test mode is initiated in the dice. Once testing is complete, the fuse may be blown, and a ground voltage applied to the test mode enable bond pads through the ground pins so the resistor disables the test mode in the dice and initiates an operational mode. As a result, dice packaged in IC modules may be tested after packaging.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: May 29, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, James M. Wark, Eric S. Nelson, Kevin G. Duesman
  • Patent number: 6233708
    Abstract: A frame error detection method includes the steps of determining a plurality of comparison values which include a given comparison value depending on a frame energy of a given speech frame or a change in frame energy between the given speech frame and a preceding speech frame. The given speech frame is identified as a bad speech frame if a logical combination of a plurality of criteria is met. One of the criteria is based on a comparison of a threshold value with the given comparison value depending on the frame energy or the change in frame energy. A device for frame error detection and a receiver including the device for frame error detection are also provided.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: May 15, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Hindelang, Christian Erben, Wen Xu
  • Patent number: 6230296
    Abstract: The invention is directed to an error correction scheme used in a computer system where data is provided from a service to a terminal. The data is dynamically changing, and the user is interested more in a final or current state of the data than in intermediate states. Data is provided in a stream of blocks with sequential “sequence” numbers associated with each block. The invention assumes that the data provider transmits data blocks in order of sequence. The terminal tracks the sequence numbers of incoming blocks. When the terminal finds that one or more blocks have been skipped or are missing, the terminal sends a request to the central source for update data. Unlike prior art systems, which request that the missing block or blocks be re-sent, the present invention requests that the information contained in the missing command be provided, for example the current data at the display area associated with the missing block.
    Type: Grant
    Filed: April 20, 1998
    Date of Patent: May 8, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: James G. Hanko, Alan T. Ruberg
  • Patent number: 6230286
    Abstract: A mechanism is provided for a failed computer system to send a report of the failure to a remote site without dependency on a service processor or maintenance processor. The computer system is capable of reporting system failure to a remote site independent of whether the system may be successfully rebooted. The system includes a CPU, and, coupled to the CPU, a non-volatile control store, a main memory, a storage device storing a computer operating system, and a data modem. Firmware is resident in the non-volatile control store of the main computer system for reporting system failure to a remote site independent of whether the system may be successfully rebooted by reloading the operating system into main memory. The firmware is invoked upon occurrence of a non-recoverable error and provides for assembling failure-related information, establishing communication with the remote site, and transmitting the failure-related information to the remote site.
    Type: Grant
    Filed: March 21, 1995
    Date of Patent: May 8, 2001
    Assignee: Siemens Information and Communication Products LLC
    Inventors: Robert Shapiro, Paul Andrew Dorwin
  • Patent number: 6226769
    Abstract: A computationally simple yet powerful forward error correction code scheme for transmission of real-time media signals, such as digitized voice, video or audio, in a packet switched network, such as the Internet. The invention appends to each of a series of payload packets a single forward error correction code that is defined by taking the XOR sum of a preceding specified number of payload packets. The invention thereby enables correction from the loss of multiple packets in a row, without significantly increasing the data rate or otherwise delaying transmission.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: May 1, 2001
    Assignee: 3Com Corporation
    Inventors: Guido M. Schuster, Jerry Mahler, Ikhlaq Sidhu, Michael Borella
  • Patent number: 6216246
    Abstract: This invention provides practical methods to make a DRAM fully compatible with existing SRAM products. This is accomplished by design and manufacture methods according to the invention, which includes a method to reduce standby power of reference voltage generators and a method to avoid the alpha particle problem using a novel error correction code (ECC) mechanism. The reference voltage generator of the present invention can adjust the values of output voltage and driving power separately following simple procedures. It has very strong driving power to maintain the reference voltage, which is necessary to support high-speed operation of memory devices of the present invention. In the mean time, its standby power can be reduced by orders of magnitudes using simple control mechanism, which is necessary to make our memory device compatible with the properties of existing SRAM products. There is no need to use feedback circuits or operation amplifiers, so the circuit is extremely stable and reliable.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: April 10, 2001
    Inventor: Jeng-Jye Shau
  • Patent number: 6209111
    Abstract: First and second instances of a message are received over a wireless connection. It is determined whether the first and second instances of the message contain an error. If both instances contain an error, an error free instance of the message is reconstructed from the two erroneous instances by merging portions of the first and second instances.
    Type: Grant
    Filed: November 9, 1998
    Date of Patent: March 27, 2001
    Assignee: Microsoft Corporation
    Inventors: Don Kadyk, Vinay Deo, Michael J. O'Leary
  • Patent number: 6209114
    Abstract: A programmable logic device, such as a digital signal processor (DSP) (130), having a Chien search unit (116) is disclosed. The Chien search unit (116) is arranged to perform finite field arithmetic functions useful in identifying roots of a polynomial, as is useful in Reed-Solomon decoding, particularly, after the execution of a Euclidean array function. Galois field multipliers (306) perform finite field multiplication of coefficient values (&Lgr;) and powers of symbol values (&agr;); the products of such multiplications are written into the coefficient register (304) for use in connection with the next symbol value. Finite field adders (308, 310; 318, 320) produce a final sum that is interrogated by zero detection circuitry (206) to determine whether a root is presented by the current symbol value.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: March 27, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Tod D. Wolf, Jonathan H. Shiell
  • Patent number: 6205566
    Abstract: In a semiconductor integrated circuit, a select signal output circuit switches a selector to take in the output of a circuit section in response to a signal “0” received at the D terminal thereof during normal operation. Thus, a scan flip-flop receives the output of the circuit section. During a scan test mode, a select signal “0” or “1” is input through a scan-in terminal to the select signal output circuit and then to the selector. If the select signal is “0”, then the selector selects the output of the circuit section. On the other hand, if the select signal is “1”, then the selector selects a clock signal supplied from a clock signal generator. The output of the circuit section or the clock signal supplied from the clock signal generator, which has been input to the scan flip-flop, is passed through a scan path and output to the outside through a scan-out terminal.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: March 20, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Sadami Takeoka
  • Patent number: 6205567
    Abstract: A fault simulation method in which a sufficient diagnostic rate is ensured by enabling a fault in a circuit area forward of a storage element to be handled as an object to be detected, to thereby increase the speed of detection of a fault; i.e., the speed of fault simulation. In the fault simulation method, the integrated circuit is divided into a backward circuit area, which is a combinational circuit area on the output-pin side of a storage element included in the integrated circuit, and a forward circuit area, which is a combinational circuit area on the input-pin side of the storage element. When a fault which propagates to input pins of the storage element exists in the forward circuit area, the value of the fault at that observation time is written into the storage element, and at a later observation time the value of the fault is read from the storage element and propagated to the backward circuit area from output pins of the storage element.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: March 20, 2001
    Assignee: Fujitsu Limited
    Inventor: Daisuke Maruyama
  • Patent number: 6202180
    Abstract: A memory for controlling a display and which relieves a memory cell by exchanging an address when the memory has defective portions, including an external address input; a first memory circuit which stores an address corresponding to a specified portion of a display; a second memory circuit which stores an address provided to be faulty as a result of a test; and address converting circuit coupled to the external address input and the first and second memory circuits. The converting circuit outputs the address stored in the second memory circuit when an address supplied from the external address input coincides with the address stored in the first memory circuit and outputs the address stored in the first memory circuit when the address supplied from the external address input coincides with the address stored in the second memory circuit.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: March 13, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeru Nose
  • Patent number: 6202183
    Abstract: An improved system and method to ensure the testability of any analog cell embedded in a mixed signal IC is described wherein the testability is independent of the core logic of that IC, which does not require the dedication of any pin solely to the testing of that IC. A uniform analog test access port design simplifies chip layout, greatly reduces the nunber of MUXed pins required, and allows generation of an analog test program for the total chip which is a simple concatenation and re-use of the individual analog cell test programs.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: March 13, 2001
    Assignee: Philips Semiconductors Inc.
    Inventors: Bernard Ginetti, Christian Zotier, Olaf Granzow
  • Patent number: 6202186
    Abstract: An integrated circuit tester includes a host computer, a pattern generator and a set of tester circuits for performing a series of tests on an integrated circuit. The pattern generator is programmed to supply a sequence of pattern data as input to the tester circuits for controlling their operations during each test of the series. The pattern generator may also be programmed to interrupt the host computer before or during any test whenever it is necessary for the host computer to carry out an activity. The host computer may be programmed to respond to an interrupt by writing parameter control data into the tester circuits to reconfigure their operating characteristics, by acquiring test results from the tester circuits, or by directly controlling tester circuit operations during a test. When necessary to provide sufficient time for the host computer to carry out its task, the pattern generator may be programmed to temporarily suspend supplying pattern data to the tester circuits after sending an interrupt.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: March 13, 2001
    Assignee: Credence Systems Corporation
    Inventor: John Mark Oonk
  • Patent number: 6202182
    Abstract: A method of built-in self-testing field programmable gate arrays (FPGAs) including the programmable logic blocks, the programmable routing networks and the programmable input/output cells or boundary ports at the device, board or system level includes testing the programmable logic blocks, reconfiguring a first group of he programmable logic blocks to include a test pattern generator and an output response analyzer, and configuring the programmable routing network into groups of wires under test. This step is followed by generating test patterns propagated along the wires under test and comparing the outputs utilizing the output response analyzer. Based on the result of the comparison a pass/fail test result indication is routed to the associated boundary port. The results from a plurality of output response analyzers can be compared utilizing an iterative comparator in order to reduce the number of boundary ports required during testing.
    Type: Grant
    Filed: June 30, 1998
    Date of Patent: March 13, 2001
    Assignee: Lucent Technologies Inc.
    Inventors: Miron Abramovici, Charles Eugene Stroud, Sajitha S. Wijesuriya
  • Patent number: 6199188
    Abstract: A system determines the locations of four errors in a code word over GF(2m), for any m, by transforming a degree-four error locator polynomial &sgr;(x) ultimately into two quadratic equations, finding the solutions of these equations, and from these solutions determining the roots of the error locator polynomial. The system first manipulates the degree-four error locator polynomial into a polynomial &thgr;(y) that has a coefficient of zero for the degree-three term. The system then factors this polynomial into two degree-two factors with four unknown variables. The system expands the factors and represents the coefficients of &thgr;(y) as expressions that include the four unknown variables, and manipulates the expressions to produce a degree-three polynomial with only one of the unknown variables. The system next solves for that variable by finding a root of the degree-three polynomial in GF(2m) if the field is an even-bit field or in an even-bit extension of GF(2m) if the field is an odd-bit field.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: March 6, 2001
    Assignee: Quantum Corporation
    Inventors: Ba-Zhong Shen, Lih-Jyh Weng
  • Patent number: 6199182
    Abstract: The input and output buffers and related peripheral circuits, such as holding circuits and ESD circuits, of an integrated circuit are tested using the boundary scan paths and three additional test bond pads. This structure provides for testing these circuits without the need physically to contact the functional bond pads. For an output buffer, one switch opens the connection between the output of the functional circuits and the input of the output buffer. A second switch connects the first test bond pad to the input of the output buffer. A third switch connects the second test bond pad to the output of the output buffer. A fourth switch connects the third test bond pad to the output of the output buffer. For an input buffer, separate first and second switches respectively connect the second and third test bond pads to the input of the input buffer. A third switch connects the first test bond pad to the output of the input buffer.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: March 6, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 6199184
    Abstract: A parallel signature compression circuit includes two or more MISRs (multiple input signature registers) coupled in series. The signature compression circuit allows the error effect of at least one of two repetitive error patterns to be transferred to a cell other than the cell where the error effect is counterbalanced. In an embodiment, a signature compression circuit has two MISRs and prevents the error masking due to the repetitive error patterns of the odd-numbered distances. In another embodiment, in order to reduce the error masking by the repetitive error patterns with even-numbered distances, the repetitive error patterns are compressed as many times as possible within the range of design rule.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: March 6, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Gyoo-Chan Sim