Abstract: In an N-bit address trap comparator, an N-bit address trap register stores an N-bit reference address, a bit-by-bit comparator compares an N-bit address with the N-bit reference address bit-by-bit, and an all-bit comparator detects whether or not all outputs of the bit-by-bit comparator have the same value. In a test mode the N-bit reference address is reset so that a first bit of the N-bit reference address is caused to be a first binary value and other bits are caused to be a second binary value. Also, the second binary value is set in all bits of the N-bit address, and then, the N-bit reference address is shifted within the N-bit address trap register.

Abstract: A memory card design which adds parity for non-parity computer systems to supply error detection capabilities is provided. The apparatus includes a memory card, parity DRAM locatable on the memory card, logic for generating and checking parity bits and logic for the control of the generating, checking and storing parity bits. Also, in another embodiment, the apparatus adds error correction code to the memory card to provide error detection and correction code to systems lacking such capabilities.

Abstract: A device for testing the fixability of logic circuits having an embedded memory. The logic circuit includes a built-in test circuit for generating data which tests the embedded memory. An allocation logic circuit provides an output line for each bit of the memory identifying if the bit has either failed or passed. A Failed Data Bit Register is connected to the output lines. The Failed Data Bit Register includes a plurality of shift register stages. A multiplex circuit associated with each stage of the shift register receives as a first input the corresponding output line of the allocation logic circuit. A second input of the multiplex circuit connects to the preceding stage of the shift register. A clock cycle counter connects to an enabling line of the multiplex circuits and to a source of clock pulses.

Abstract: A method and system for controlling a dynamic nonlinear plant. An input signal controls the plant and an output signal represents a state of the plant in response to the received input signal. A memory stores input and output signals corresponding to m consecutive past states of the plant. A computer neural network predicts a set of future output states representative of the output signal corresponding to the next n consecutive future states of the plant in response to a set of trial control inputs. The trial control inputs represent the input signal corresponding to the next n consecutive future states of the plant. The neural network predicts the future output states based on the past input and output signals and the future trial control inputs. A processor generates the trial control inputs and determines a performance index, indicative of plant performance over time in response to the trial control inputs, as a function of the future output states.

Abstract: A method and apparatus are provided for functionally verifying an integrated circuit design. A hardware-oriented verification-specific object-oriented programming language is used to construct and customize verification tests. The language is extensible, and shaped to provide elements for stimulating and observing hardware device models. The invention is platform and simulator-independent, and is adapted for integration with Verilog, VHDL, and C functions. A modular system environment ensures interaction with any simulator through a unified system interface that supports multiple external types. A test generator module automatically creates verification tests from a functional description. A test suite can include any combination of statically and dynamically-generated tests. Directed generation constrains generated tests to specific functionalities. Test parameters are varied at any point during generation and random stability is supported.

Abstract: A system and method are provided that permit an accurate checksum to be generated of a block of data being transmitted via a prefetched bus, despite repeated transmissions of identical portions of the block and presentation of those identical to checksum logic simultaneously with their transmission by the bus, by ensuring that only those portions of the data block that have yet to be checksummed are checksummed.

Abstract: A system and method for regulating data transmission between a source node and a destination node is disclosed herein. The present method contemplates monitoring system performance so as to detect when the system enters an overloaded state. Such detection may be effected by, for example, determining the extent of the time interval during which instructions are retained in a queue at the destination node awaiting execution. When this interval exceeds a maximum queuing time, the system is deemed to be in an overloaded state. Upon entry into an overloaded state, data transmission from the source node is suspended pending recovery of the system from the overloaded state. In a preferred implementation, overload probe messages are periodically inserted into a message queue at the destination node.

Abstract: A method for encoding a channel using a parallel convolutional encoder is disclosed. The method includes the steps of a first step for performing an encoding operation using a parallel convolutional encoder at the time when a data is inputted into a frame input data register for implementing a channel encoding operation and generating a code symbol, and a second step for storing the thusly generated code symbol into an interleaver RAM which is alternately selected by the frame unit.

Abstract: A semiconductor device having a self test circuit including an embedded dynamic random access memory array for storing data, a self test controller for internally generating test data patterns and expected resulting data and for comparing the expected resulting data with actual resulting data, test interface circuitry for loading the test data patterns into the memory and reading back the actual resulting data from the memory, means for selectively programming a voltage level to be applied to a selected cell plate of the memory according to predetermined test requirements and means for storing an address of a defective memory cell. In addition, the semiconductor device includes means for repairing a defective memory row or column in response to a signal received from the self test controller.

Abstract: First and second digital data to which a code to correct errors was added are inputted. For a certain period of time, processes to detect errors in the first and second digital data are executed in accordance with the order of the first digital data and the second digital data. In this period of time, on the basis of the processing results, processes to correct the errors in the first and second digital data are executed in accordance with the order of the second digital data and the first digital data. Thus, the error detecting processes of the digital data that is inputted on a predetermined unit basis can be executed in parallel and an error correcting process in which a circuit scale is small and costs are low can be realized.

Abstract: A multiple bank memory device is described which can be tested by accessing the multiple memory banks simultaneously. The memory includes a test mode trigger which initiates a test which writes and reads from memory cells located in different memory banks. Error detection circuitry evaluates data read from different memory banks and determines if a defect is present in the memory cells. Different test patterns and techniques are described for identifying defective memories.

Abstract: The scan flip-flop that controls a bi-directional or a switchable high-impedance driver is implemented so that, when a logic value on a first input is latched in response to a first clock signal, and a logic value on a second input is latched in response to a second clock signal, both logic values are output during the second clock period.

Abstract: The invention relates to a method for decreasing the frame error rate of information to be transmitted in the form of data frames in a data transmission system, in which the information to be transmitted is divided into data frames (102, 202). The data frame (102, 202) is supplemented with error correction data generated by using part of the information to be transferred. At least part of the information to be used in the generation of error correction data is protected by error correction coding (107, 206), by which an error correction coded data frame (108, 207) is obtained, in which different parts of the protected information have different error rates (BER). The error correction coded data frames (111, 212) are transferred in the data transmission channel from the transmitter to the receiver.

Abstract: The present invention concerns a method and system for protection against corruption of data. In order to backup files to be stored in a storage medium, a set of redundant parity symbols is computed by encoding cross-sections across said files using a systematic code. These parity symbols and the files are then stored for later retrieval. If some of these files are erased, corrupted, damaged or infected by a virus, they are reconstructed by decoding the surviving files and the parity symbols.

Abstract: An on-chip test circuit in an integrated circuit memory device includes a test mode terminal and a test data storage circuit having an input coupled to a data terminal of the memory device and an output coupled to a memory-cell array in the memory device. The storage circuit further includes terminals adapted to receive respective read test data and write test data signals. The storage circuit stores bits of data applied on the data terminal when the write test data signal is active. The storage circuit provides on its output the bits of stored data when the read test data signal is active. An error detection circuit includes a first input coupled to the memory-cell array and a second input coupled to the output of the storage circuit. The error detection circuit develops an active error signal on an output when the data on its input is unequal. A test control circuit is coupled to the terminals of the test data storage circuit, and to the test mode terminal.

Abstract: A memory addressing scheme suitable for use for either interleaving or de-interleaving data bytes of, e.g., a broadcast digital television (DTV) data stream. A number of memory branches are configured in a random access memory (RAM), wherein at least some of the branches have different numbers of memory locations for reading out and for storing data bytes, thus defining memory branches of different lengths in the RAM. A start address is determined for each of the memory branches in the RAM, corresponding to a first memory location of each branch. An offset value is determined for each memory branch, to be added to the start address for the branch for addressing a memory location of the branch. If an offset value does not exceed the length of a corresponding branch, an address corresponding to the sum of the branch start address and the offset value is generated for addressing a successive memory location of the branch, and the offset value for the branch is incremented by one.

Abstract: A system clock switch circuit for a computer main board sends a reset signal to the chipset from the clock generator or a additional reset signal generator as soon as the system clock frequency is changed by the CPU. In result, the computer main board restarts with a new system clock frequency after the reset signal is canceled to avoid the malfunctions caused by the non-synchronization between the system clock frequency and the clock frequencies of peripherals.

Abstract: When an interrupt request signal is input, a microprocessor checks, upon termination of an instruction cycle being executed, whether the interrupt request is masked. If the interrupt request is not masked, the microprocessor saves the content of the program counter and the processor status register to a stack. If an extended interrupt request signal is at a high level, the microprocessor sets the bus status signals to a unique state so that a data bus is in a high impedance state. An interrupt controller outputs mask flag data to the data bus so that the mask flag data is saved to a stack. Thereafter, the three-byte data is fetched from a vector address and stored in the program counter. When the mask flag data is to be restored, the mask flag data is read while the bus status signals are set to the unique state.

Abstract: A system for transmitting data over an erasure channel. A data block is divided into coarse and fine segments. The coarse segment is encoded using an error-correcting encoding process. The fine segment and the encoded coarse segment are combined and divided into packets, and the packets are transmitted over the erasure channel. When the data is received, the coarse segment is decoded. If data packets were lost during transmission, the coarse segment is reconstructed as the received data block. If no packets were lost, the fine segment is combined with the coarse segment and the entire data block as originally transmitted is reconstructed. For large numbers of packets, the system invention can achieve any point within the capacity region of an erasure channel.

Abstract: A method in a data processing system for automatically terminating or resuming backup copy sessions after an abnormal interrupt or reset notification occurrence during a backup copy process. A status indication is entered into activity tables associated with a plurality of storage subsystems and devices within a data processing system in response to initiation of a backup copy session. Status indications are then entered upon successful completion of a backup copy session within the data processing system. The indications within the activity tables are reviewed to determine the status of a backup copy session upon restarting a resource manager, abnormal termination of a backup copy program, or an operating system initial program load. If a backup copy session has been initiated but not completed, the backup copy session is then terminated. The indications within the activity tables are also reviewed to determine the status of a backup copy session if a reset notification is raised by a storage subsystem.