Abstract: A packet transfer scheme for realizing a control of a packet inspection device to pass only packets from those mobile computers that can be recognized as authenticated among non-management target mobile computers that had moved inside the network, to outside the network.

Abstract: The present invention reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more "planes." Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word having address bits A0-RA9) is received by and controls the multiplexer to select between the two banks of fuses. Additionally, the planes span blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory.

Abstract: A data communication method and system that, when performing real-time type data communication using the same code configuration as for storage type communication wherein error correction is done by retransmission, improve the performance of error correction by using error detection codes effectively, avoiding inefficient-use of the error detection codes, and enhance the quality of the data transmitted. In a detection/correction selector unit (27), a reply frame production unit (31) is directed to request retransmission of error frames discarded by an error detector unit (29) when conducting storage type data communication, while data are twice error-corrected by a second error correction unit (24) and a first error correction unit (28), and are output to a data output unit (30) when conducting real-time type data communication.

Abstract: A boundary scan based VIH/VIL test scheme for a clock forwarded interface of an IEEE 1149.1 Standard-compliant electronic component is provided. The Standard-compliant component has a test access port (TAP) and a forwarded clock interface including data and forwarded clock inputs for receiving signals from and sending signals to external circuitry during a test operation. Connected to each of such component's data inputs is a clocked and an unclocked input buffer. Coupled to the TAP is an instruction register for receiving Standard defined and other test instructions provided by the external circuitry at the TAP. Also coupled to the TAP is a chain of boundary scan cells, each associated with a different one of the input pins and connected to the output of each input buffer coupled thereto, and a TAP controller for generating control signals to capture and shift data through the boundary scan cells in response to test instructions received by the instruction register.

Abstract: A test pattern generator for a semiconductor integrated circuit tester comprises a DRAM for receiving and storing test pattern data in blocks and a SRAM for storing checking data in units, wherein each unit of checking data stored in the SRAM bears a predetermined relationship to a corresponding block received by the DRAM. A DRAM sequencer addresses the DRAM for reading the blocks of test pattern data in a predetermined order and a SRAM sequencer addresses the SRAM for reading the units of checking data from the SRAM. A validating circuit receives a block of test pattern data read from the DRAM and the corresponding unit of checking data read from the SRAM and provides an output which indicates whether the unit of checking data is in the predetermined relationship with the block.

Abstract: An implementation of sensor-driven run-to-run process control for semiconductor wafer fabrication integrates a robust, automated Fourier transform infrared reflectometer onto a wafer fabrication cluster tool. Cell controller software integrates an adaptive run-to-run controller, process tool recipe upload and download through a SECS port, sensor control, data archiving, and a graphical user interface.

Abstract: A personal authentication system provides at least two levels of security for an authentication process, in addition to numerous other security features. The system operates across many different software and hardware platforms, in a client/server fashion, employing a challenge/response process that does not require users to transmit their passwords across a network. An application running on a client computer is coupled with an application running on a server computer. The client generates a response to a challenge, which is provided by the server. The response is a combined function of the server's challenge, a serial number assigned to the client, and a password provided by the user.

Abstract: A printed circuit board assembly testing device includes a LISN device connected to a power source and to a test enclosure. The test enclosure includes a power supply and a communication port. A signal analyzer is interfaced to the LISN device. A circuit board assembly unit under test is positioned in the test enclosure. A controlling computer is interfaced to the communication port. The controlling computer includes a hard disk storage device having benchmark data stored therein. A communication bus interconnects the controlling computer to the signal analyzer. The unit under test is powered up and emissions data is observed which correlates to activity in the unit under test. The emissions data is compared to the benchmark data and a determination can be made as to whether the observed data meets the benchmark data within an acceptable tolerance.

Abstract: A write driver circuit includes a drive circuit having a first drive node adapted to receive a first voltage, a second drive node, an input adapted to receive a data signal, and an output. The drive circuit couples the output to the first voltage node when the data signal has a first logic voltage, and couples the output to the second drive node when the data signal has a second logic voltage. A test circuit has an input adapted to receive a test mode signal, and an output coupled to the second drive node. The test circuit develops a first impedance between the second drive node and a second voltage source when the test mode signal is active, and develops a second impedance between the second drive node and the second voltage source when the, test mode signal is inactive.

Abstract: A testing system evaluates one or more integrated circuit chips using RF communication. The system includes an interrogator unit with a radio communication range, and an IC chip adapted with RF circuitry positioned remotely from the interrogator unit, but within the radio communication range. The interrogator unit transmits a power signal to energize the IC chip during test procedures, and interrogating information for evaluating the operation of the IC chip. Test results are transmitted by the IC chip back to the interrogator unit for examination to determine whether the IC chip has a defect. In this manner, one or more IC chips can be evaluated simultaneously without physically contacting each individual chip.

Abstract: The invention relates to a multi-output monolithic device, and particularly to a multi-output monolithic integrated circuit device without generating a simultaneous switch output (SSO) in communication or in a network, in which the plurality of output port will not switch from "0" to "1" or from "1" to "0" simultaneously to prevent insufficient power supply caused by a simultaneous switch, resulting in noise generation and errorous operations. A multi-bit shift register in used in the invention to make each output port have a different and to reduce the probability of the same output value on each output port, thereby reducing the influence of SSO. Then, a slightly different delay is made of each output port during output, so as to eliminate SSO.

Abstract: A JTAG Boundary Scan method by which the on-chip system logic (OCSL) of an integrated circuit is changed by use of a state machine which, among other functions, allows a predefined set of instructions to be loaded into an Instruction Register and then executed. The predefined instructions are designed to follow in sequence after certain other previous instructions. The instructions change the OCSL from one state to another state and allows the state to be changed without the need of a full device reset. Additional instructions within this invention were created to have attendant operating modes for which termination is self timed within the integrated circuit. Additional instructions further control the implementation of instruction execution within the state machine.

Abstract: A system decoder having error correcting memories for high-speed data transmission and a method for controlling the same. A system decoder of an optical disk reproducing apparatus having a descrambler for restoring scrambled data in the process of encoding data, includes first and second memories for correcting an error, and a memory controller for transmitting error-corrected data to the descrambler while data read and demodulated from the optical disk is written in one of the first and second memories, and error-correcting data written in the other memory while the demodulated and error-corrected data is written and read.

Abstract: An error correcting method reducing the time needed to provide error correction using a buffer memory. The method includes performing row error correction by using a plurality of rows of data to produce row-corrected block data and performing column error correction by using the plurality of columns of data to produce column-corrected block data. In addition, at least one of the performing row error correction and performing column error correction operates using a plurality of rows or columns of data in units of a predetermined number of rows or columns so as to provide error correction for the plurality of rows or columns in parallel.

Abstract: There is provided a memory testing apparatus for testing an IC memory having a failure relief line or lines, which is constructed to sufficiently serve to test using a failure analysis memory having its storage capacity of two times that of a memory under test. An extended storage area having its storage capacity approximately equal to that of a memory under test MUT is provided in a failure analysis memory having a main storage area whose storage capacity is the same as that of the memory under test adjacent to one side of the main storage area in either one of the row address direction (X coordinate direction) or column address direction (Y address direction) thereof.

Abstract: A pattern generator for an integrated circuit tester includes an instruction memory storing addressable instructions (INST) and reading out each instruction when addressed by an address (ADDR) supplied as input thereto. An instruction processor receives each instruction read out of the instruction memory and alters the address input to the instruction memory in accordance with the received instruction so that the instruction memory reads out a next instruction. The instruction processor, which includes a conventional return address stack, is capable of executing conventional address increment, call and return instructions. The instruction processor is also capable of executing a temporary return instruction (TEMP) by incrementing its current address output to produce a new return address, by setting its address output to the value of a return address previously saved in the stack, by popping the saved return address from the stack, and by pushing the new return address onto the stack.

Abstract: In a failure analysis memory for memory testing apparatus which has a failure data storage part composed of a failure data memory and a first memory control part and a mask data storage part composed of a mask data memory and a second memory control part, when the logical comparison result by the testing apparatus is a failure in the test mode, the first memory control part effects control to generate write enable data and write failure data in the failure data memory at the corresponding address and, in the remove mode, effects control to read out failure data from the failure data memory and provide it to the mask data storage part.

Abstract: A method, circuit and apparatus is provided for preserving and/or correcting product engineering information. Non-volatile storage devices reserved for receiving product engineering bits can either be contained in at least three separate storage locations spaced from each other across the integrated circuit or, alternatively, be contained in a single storage location area with error correction bits and/or words added to that location. In the first instance, redundant product engineering bits are written to each storage location. Product engineering bits read from a majority of those locations which have identical values are deemed valid. The addition of extra bits and/or words can be combined with the possibly defective product engineering bits to correct errors in those bits.

Abstract: The present invention is embodied in a method and apparatus which provides a ROM embedded in an DRAM utilizing unused portions of the DRAM. By hardwiring the unused digitlines of the DRAM to either a specified voltage or ground, the outputs of the sense amplifiers associated with those unused digitlines can be programmed to output a specific logic state. By combining the outputs from several sense amplifiers, a fixed bit pattern can be produced. The fixed bit pattern can be used, for example, to generate a test data pattern for a Built-in Self Test or to generate an initialization sequence.

Abstract: A computationally efficient, machine-implementable method and means for detecting and correcting errors in received codewords on-the-fly within the capacity of a linear cyclic code using ultra-fast error location processing. Each error locator polynomial of degree t over a finite Galois field derived from a codeword syndrome is mapped into a matrix representative of a system of linear simultaneous equations related to the polynomial coefficients. Roots indicative of error locations within the codeword are extracted from the matrix by a modified Gaussian Elimination process for all the roots where t.ltoreq.5 and at least one root plus a subset of candidate roots from the finite field for iterative substitution where t>5. Corrected values are separately determined and correction is secured by logically combining the corrected values with the codeword values in error at the error locations represented by the roots.