Patents Examined by Albrecht
  • Patent number: 11107845
    Abstract: A Thin Film Transistor (TFT) substrate includes a first semiconductor film, a first electrically conductive member provided in a layer higher than the first semiconductor film, an interlayer insulating film provided in a layer higher than the first electrically conductive member and including a first through hole, a second semiconductor film provided in a layer higher than the interlayer insulating film, a second electrically conductive member provided in a layer higher than the second semiconductor film, an organic insulating film provided in a layer higher than the second electrically conductive member and including a second through hole, and a third electrically conductive member provided in a layer higher than the organic insulating film. A contact hole extends through the first and the second through hole to the first electrically conductive member.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 31, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Hirohiko Nishiki, Takeshi Yaneda
  • Patent number: 11100857
    Abstract: [Object] To provide a display device that displays a display image with high resolution and higher uniformity, and an electronic apparatus including the display device. [Solution] A display device including: a driving transistor including a first-conductivity-type activation region provided in a semiconductor substrate, an opening provided to cross the activation region, a gate insulating film provided on the activation region including an inside of the opening, a gate electrode filling the opening, and second-conductivity-type diffusion regions provided on both sides of the activation region across the opening; and an organic electroluminescent element configured to be driven by the driving transistor.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: August 24, 2021
    Assignee: Sony Corporation
    Inventor: Shimpei Tsujikawa
  • Patent number: 11092836
    Abstract: The present invention discloses an array substrate, including: a first metal layer, a second metal layer and a common electrode layer which are insulated from each other and sequentially formed on a base substrate; the first metal layer includes a gate line, the second metal layer includes a data line, and the common electrode layer includes a touch sensing electrode; the second metal layer includes a touch signal line, the touch signal line is electrically connected to the touch sensing electrode, and the touch signal line and the data line are intersected each other and are disconnected at an intersection location; and the first metal layer includes a bridging connection line, two ends of the bridging connection line are connected to the touch signal line such that the touch signal line disconnected at the intersection location are electrically connected. A manufacturing method and an in-cell touch panel are also disclosed.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 17, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Pengfei Yu, Jiawei Zhang
  • Patent number: 11088280
    Abstract: The disclosure provides for a transistor which may include: a gate stack on a substrate, the gate stack including a gate dielectric and a gate electrode over the gate dielectric; a channel within the substrate and under the gate stack; a doped source and a doped drain on opposing sides of the channel, the doped source and the doped drain each including a dopant, wherein the dopant and the channel together have a first coefficient of diffusion and the doped source and the doped drain each have a second coefficient of diffusion; and a doped extension layer separating each of the doped source and the doped drain from the channel, the doped extension layer having a third coefficient of diffusion, wherein the third coefficient of diffusion is greater than the first coefficient of diffusion and the second coefficient of diffusion is less than the third coefficient of diffusion.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 11088177
    Abstract: The invention provides an array substrate and manufacturing method thereof.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: August 10, 2021
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Liwang Song, Zhaohui Li
  • Patent number: 11081482
    Abstract: A method of fabricating adjacent vertical fins with top source/drains having an air spacer and a self-aligned top junction, including, forming two or more vertical fins on a bottom source/drain, forming a top source/drain on each of the two or more vertical fins, wherein the top source/drains are formed to a size that leaves a gap between the adjacent vertical fins, and forming a source/drain liner on the top source/drains, where the source/drain liner occludes the gap between adjacent top source/drains to form a void space between adjacent vertical fins.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 11069720
    Abstract: Disclosed are a display panel and a display device, and the display panel includes a display area and a non-display area adjacent to the display area, the display area includes a first display area and a second display area, and the number of pixels in each column of pixels in the first display area is less than that of pixels in any column of pixels in the second display area.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: July 20, 2021
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Baosheng Tao, Zhiyong Xiong, Liyuan Liu
  • Patent number: 11043450
    Abstract: An anti-fuse structure, a method for fabricating the anti-fuse structure, and a semiconductor device are disclosed. The anti-fuse structure includes a semiconductor substrate, a fuse oxide layer, a gate material layer, a first electrode and a second electrode. An active area is defined on the semiconductor substrate by an isolation structure. The active area includes a wide portion and a narrow portion connected to each other. The fuse oxide layer is located on the semiconductor substrate, covers the narrow portion and extends to cover a first part of the wide portion. The gate material layer is formed on the fuse oxide layer. The first electrode is formed on and electrically connected to the gate material layer, while the second electrode is formed on and electrically connected to a second part of the wide portion not covered by the fuse oxide layer.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 22, 2021
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Chih Cheng Liu
  • Patent number: 11024712
    Abstract: A semiconductor device is proposed. The semiconductor device includes a source region of a field effect transistor having a first conductivity type, a body region of the field effect transistor having a second conductivity type, and a drain region of the field effect transistor having the first conductivity type. The source region, the drain region, and the body region are located in a semiconductor substrate of the semiconductor device and the body region is located between the source region and the drain region. The drain region extends from the body region through a buried portion of the drain region to a drain contact portion of the drain region located at a surface of the semiconductor substrate, the buried portion of the drain region is located beneath a spacer doping region, and the spacer doping region is located within the semiconductor substrate.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 1, 2021
    Assignee: Intel IP Corporation
    Inventors: Vase Jovanov, Peter Baumgartner, Gregor Bracher, Luis Giles, Uwe Hodel, Andreas Lachmann, Philipp Riess, Karl-Henrik Ryden
  • Patent number: 11018164
    Abstract: A thin-film transistor substrate includes a thin-film transistor and a light-shielding part. The thin-film transistor includes a gate electrode, a semiconductor part made from a semiconductor material and superimposed on a part of the gate electrode via a first insulating film, a source electrode on a part of the semiconductor part and connected to the semiconductor part, and a drain electrode on a part of the semiconductor part and connected to the semiconductor part with spaced apart from the source electrode. The light-shielding part includes a first light-shielding section disposed above the semiconductor part, the source electrode, and the drain electrode via the second insulating film and superimposed on the semiconductor part, and a second light-shielding section not to be superimposed on the gate electrode, the source electrode, and the drain electrode and having an opening adjacent to the thin-film transistor.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 25, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Masahiro Yoshida
  • Patent number: 11018257
    Abstract: An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: May 25, 2021
    Inventors: Yu-San Chien, Hsin-Che Chiang, Chun-Sheng Liang, Kuo-Hua Pan
  • Patent number: 11004873
    Abstract: An array substrate and a display device are disclosed. The array substrate includes: a base substrate; and a first electrically conductive layer and a second electrically conductive layer on the base substrate; wherein the base substrate is provided with at least one thin film transistor, each of the at least one thin film transistor includes a gate electrode disposed in the first electrically conductive layer, and a source electrode and a drain electrode disposed in the second electrically conductive layer; and wherein, at least one of the drain electrode and the source electrode includes an electrode body and an extending portion, the electrode body overlapping with the gate electrode, and the extending portion overlapping with a portion of the first electrically conductive layer other than the gate electrode.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: May 11, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jianbo Xian, Hongfei Cheng, Yong Qiao, Yongda Ma
  • Patent number: 11004870
    Abstract: A transistor structure may include a first electrode, a second electrode, a third electrode, a substrate, and a semiconductor member. The semiconductor member overlaps the third electrode and includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion directly contacts the first electrode, is directly connected to the third semiconductor portion, and is connected through the third semiconductor portion to the second semiconductor portion. The second semiconductor portion directly contacts the second electrode and is directly connected to the third semiconductor portion. A minimum distance between the first semiconductor portion and the substrate is unequal to a minimum distance between the second semiconductor portion and the substrate.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 11, 2021
    Inventors: Hyun Sup Lee, Jung Hun Noh, Keun Kyu Song, Sang Hee Jang, Byung Seok Choi
  • Patent number: 10978594
    Abstract: The invention relates to a field-effect transistor including an active zone including a source, a channel, a drain and a control gate, which is positioned level with said channel, allowing a current to flow through said channel between the source and drain along an x-axis, said channel including: a first edge of separation with said source; and a second edge of separation with said drain; said channel being compressively or tensilely strained, characterized in that said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel. The invention also relates to a process for fabricating said transistor.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 13, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Emmanuel Augendre, Maxime Argoud, Sylvain Maitrejean, Pierre Morin, Raluca Tiron
  • Patent number: 10971497
    Abstract: A memory cell includes a curved gate channel transistor, a buried bit line, a word line and a capacitor. The curved gate channel transistor has a first doped region located in a substrate, a second doped region and a third doped region located on the substrate, wherein the second doped region is directly on the first doped region and the third doped region is right next to the second doped region, thereby constituting a curved gate channel. The buried bit line is located below the first doped region. The word line covers the second doped region. The capacitor is located above the curved gate channel transistor and in electrical contact with the third doped region. The present invention also provides a memory cell having a vertical gate channel transistor, and the vertical gate channel has current flowing downward.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: April 6, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Hong-Ru Liu, Kuei-Hsuan Yu
  • Patent number: 10964795
    Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
  • Patent number: 10964783
    Abstract: A semiconductor device according to an exemplary embodiment of the present disclosure includes a substrate, an n? type layer, a plurality of trenches, a p type region, a p+ type region, an n+ type region, a gate electrode, a source electrode, and a drain electrode. The semiconductor device may include a plurality of unit cells. A unit cell among the plurality of unit cells may include a contact portion with which the source electrode and the n+ type region are in contact, a first branch part disposed above the contact portion on a plane, and a second branch part disposed below the contact portion on a plane, the plurality of trenches are separated from each other and disposed with a stripe shape on a plane.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 30, 2021
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventor: Dae Hwan Chun
  • Patent number: 10957676
    Abstract: A light emitting device (LED) package includes: a substrate having a loading surface, a mounting surface and a pair of concave portions formed at both ends of the substrate, wherein each of the concave portions has an inner surface intersecting both of the loading surface and the mounting surface; metal wirings including a pair of electrodes, which covers a portion of the loading surface and the mounting surface and the inner surface, and a conductive part disposed on the loading surface; an LED chip loaded on the conductive part; a housing having a side wall surrounding the LED chip and a supporting surface facing the loading surface; and a covering member which is disposed on the loading surface and has a closing portion overlapping at least a portion of the concave portions when viewed from above, wherein at least a portion of the supporting surface is fixed to the closing portion.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: March 23, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Masahiko Kobayakawa, Riki Shimabukuro
  • Patent number: 10944069
    Abstract: An organic electroluminescence device includes a first electrode, a hole transport region on the first electrode, a light emitting layer on the hole transport region, an electron transport region on the light emitting layer, and a second electrode on the electron transport region. The electron transport region includes an electron transport layer directly on the light emitting layer. The electron transport layer includes a first ternary compound including a halogen element.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: March 9, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dongkyu Seo, Dongchan Kim, Jiyoung Moon, Yeongrong Park, Myungchul Yeo, Jihye Lee, Hyungseok Jang, Wonjong Kim, Yoonhyeung Cho
  • Patent number: 10923506
    Abstract: An electroluminescence display device is disclosed, which may use a polysilicon thin film transistor and an oxide thin film transistor together by using a dual line with respect to a plurality of switching transistors arranged on the same line. The electroluminescence display device includes a first active layer; a first gate line arranged on the first active layer and intersecting the first active layer; a second active layer forming a channel different from that of the first active layer, arranged on the first gate line; and a second gate line arranged on the second active layer and intersecting the second active layer. The first gate line and the second gate line are overlapped with each other, and the first gate line and the second gate line supply the same gate signal.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: February 16, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventor: JeongHwan Park