Abstract: The present technology relates to a photoelectric conversion element, a measuring method of the same, a solid-state imaging device, an electronic device, and a solar cell capable of further improving a quantum efficiency in a photoelectric conversion element using a photoelectric conversion layer including an organic semiconductor material. The photoelectric conversion element includes two electrodes forming a positive electrode (11) and a negative electrode (14), at least one charge blocking layer (13, 15) arranged between the two electrodes, and a photoelectric conversion layer (12) arranged between the two electrodes. The at least one charge blocking layer is an electron blocking layer (13) or a hole blocking layer (15), and a potential of the charge blocking layer is bent. The present technology is applied to, for example, a solid-state imaging device, a solar cell, and the like having a photoelectric conversion element.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate including a front surface, a back surface opposite to the front surface, and a light-sensing region extending from the front surface into the semiconductor substrate. The image sensor device includes a light-blocking structure in the semiconductor substrate and surrounding the light-sensing region. The light-blocking structure includes a conductive light reflection structure and a light absorption structure, and the light absorption structure is between the conductive light reflection structure and the back surface. The image sensor device includes an insulating layer between the light-blocking structure and the semiconductor substrate.

Abstract: This disclosure describes optoelectronic modules, methods for manufacturing pluralities of discrete optoelectronic modules, and optoelectronic molding tools. The methods include coating a substrate wafer and a plurality of optoelectronic components with a photosensitive material, and further include exposing select portions of the photosensitive material to electromagnetic radiation. The exposed portions delineate at least in part the dimensions of the optical channels, wherein the optical channels are associated with at least one optoelectronic component. In some instances, optical elements are incorporated into the optical channels. In some instances, the exposed portions are the optical channels. In some instances, the exposed portions are spacers between the optical channels.

Abstract: A thin film transistor (TFT) array substrate is provided. The TFT array substrate includes a display device plate and a semiconductor layer disposed on the display device plate. A thickness of the semiconductor layer is less than or equal to 35 nm.

Abstract: A Thin Film Transistor (TFT) substrate includes a first semiconductor film, a first electrically conductive member provided in a layer higher than the first semiconductor film, an interlayer insulating film provided in a layer higher than the first electrically conductive member and including a first through hole, a second semiconductor film provided in a layer higher than the interlayer insulating film, a second electrically conductive member provided in a layer higher than the second semiconductor film, an organic insulating film provided in a layer higher than the second electrically conductive member and including a second through hole, and a third electrically conductive member provided in a layer higher than the organic insulating film. A contact hole extends through the first and the second through hole to the first electrically conductive member.

Abstract: [Object] To provide a display device that displays a display image with high resolution and higher uniformity, and an electronic apparatus including the display device. [Solution] A display device including: a driving transistor including a first-conductivity-type activation region provided in a semiconductor substrate, an opening provided to cross the activation region, a gate insulating film provided on the activation region including an inside of the opening, a gate electrode filling the opening, and second-conductivity-type diffusion regions provided on both sides of the activation region across the opening; and an organic electroluminescent element configured to be driven by the driving transistor.

Abstract: The present invention discloses an array substrate, including: a first metal layer, a second metal layer and a common electrode layer which are insulated from each other and sequentially formed on a base substrate; the first metal layer includes a gate line, the second metal layer includes a data line, and the common electrode layer includes a touch sensing electrode; the second metal layer includes a touch signal line, the touch signal line is electrically connected to the touch sensing electrode, and the touch signal line and the data line are intersected each other and are disconnected at an intersection location; and the first metal layer includes a bridging connection line, two ends of the bridging connection line are connected to the touch signal line such that the touch signal line disconnected at the intersection location are electrically connected. A manufacturing method and an in-cell touch panel are also disclosed.

Abstract: The disclosure provides for a transistor which may include: a gate stack on a substrate, the gate stack including a gate dielectric and a gate electrode over the gate dielectric; a channel within the substrate and under the gate stack; a doped source and a doped drain on opposing sides of the channel, the doped source and the doped drain each including a dopant, wherein the dopant and the channel together have a first coefficient of diffusion and the doped source and the doped drain each have a second coefficient of diffusion; and a doped extension layer separating each of the doped source and the doped drain from the channel, the doped extension layer having a third coefficient of diffusion, wherein the third coefficient of diffusion is greater than the first coefficient of diffusion and the second coefficient of diffusion is less than the third coefficient of diffusion.

Abstract: The invention provides an array substrate and manufacturing method thereof.

Abstract: A method of fabricating adjacent vertical fins with top source/drains having an air spacer and a self-aligned top junction, including, forming two or more vertical fins on a bottom source/drain, forming a top source/drain on each of the two or more vertical fins, wherein the top source/drains are formed to a size that leaves a gap between the adjacent vertical fins, and forming a source/drain liner on the top source/drains, where the source/drain liner occludes the gap between adjacent top source/drains to form a void space between adjacent vertical fins.

Abstract: Disclosed are a display panel and a display device, and the display panel includes a display area and a non-display area adjacent to the display area, the display area includes a first display area and a second display area, and the number of pixels in each column of pixels in the first display area is less than that of pixels in any column of pixels in the second display area.

Abstract: An anti-fuse structure, a method for fabricating the anti-fuse structure, and a semiconductor device are disclosed. The anti-fuse structure includes a semiconductor substrate, a fuse oxide layer, a gate material layer, a first electrode and a second electrode. An active area is defined on the semiconductor substrate by an isolation structure. The active area includes a wide portion and a narrow portion connected to each other. The fuse oxide layer is located on the semiconductor substrate, covers the narrow portion and extends to cover a first part of the wide portion. The gate material layer is formed on the fuse oxide layer. The first electrode is formed on and electrically connected to the gate material layer, while the second electrode is formed on and electrically connected to a second part of the wide portion not covered by the fuse oxide layer.

Abstract: A semiconductor device is proposed. The semiconductor device includes a source region of a field effect transistor having a first conductivity type, a body region of the field effect transistor having a second conductivity type, and a drain region of the field effect transistor having the first conductivity type. The source region, the drain region, and the body region are located in a semiconductor substrate of the semiconductor device and the body region is located between the source region and the drain region. The drain region extends from the body region through a buried portion of the drain region to a drain contact portion of the drain region located at a surface of the semiconductor substrate, the buried portion of the drain region is located beneath a spacer doping region, and the spacer doping region is located within the semiconductor substrate.

Abstract: A thin-film transistor substrate includes a thin-film transistor and a light-shielding part. The thin-film transistor includes a gate electrode, a semiconductor part made from a semiconductor material and superimposed on a part of the gate electrode via a first insulating film, a source electrode on a part of the semiconductor part and connected to the semiconductor part, and a drain electrode on a part of the semiconductor part and connected to the semiconductor part with spaced apart from the source electrode. The light-shielding part includes a first light-shielding section disposed above the semiconductor part, the source electrode, and the drain electrode via the second insulating film and superimposed on the semiconductor part, and a second light-shielding section not to be superimposed on the gate electrode, the source electrode, and the drain electrode and having an opening adjacent to the thin-film transistor.

Abstract: An embodiment method includes forming a semiconductor liner layer on a first fin structure and on a second fin structure and forming a first capping layer on the semiconductor liner layer disposed on the first fin structure. The method further includes forming a second capping layer on the semiconductor liner layer disposed on the first fin structure, where a composition of the first capping layer is different from a composition of the second capping layer. The method additionally includes performing a thermal process on the first capping layer, the second capping layer, and the semiconductor liner layer to form a first channel region in the first fin structure and a second channel region in the second fin structure. A concentration profile of a material of the first channel region is different from a concentration profile of a material of the second channel region.

Abstract: An array substrate and a display device are disclosed. The array substrate includes: a base substrate; and a first electrically conductive layer and a second electrically conductive layer on the base substrate; wherein the base substrate is provided with at least one thin film transistor, each of the at least one thin film transistor includes a gate electrode disposed in the first electrically conductive layer, and a source electrode and a drain electrode disposed in the second electrically conductive layer; and wherein, at least one of the drain electrode and the source electrode includes an electrode body and an extending portion, the electrode body overlapping with the gate electrode, and the extending portion overlapping with a portion of the first electrically conductive layer other than the gate electrode.

Abstract: A transistor structure may include a first electrode, a second electrode, a third electrode, a substrate, and a semiconductor member. The semiconductor member overlaps the third electrode and includes a first semiconductor portion, a second semiconductor portion, and a third semiconductor portion. The first semiconductor portion directly contacts the first electrode, is directly connected to the third semiconductor portion, and is connected through the third semiconductor portion to the second semiconductor portion. The second semiconductor portion directly contacts the second electrode and is directly connected to the third semiconductor portion. A minimum distance between the first semiconductor portion and the substrate is unequal to a minimum distance between the second semiconductor portion and the substrate.

Abstract: The invention relates to a field-effect transistor including an active zone including a source, a channel, a drain and a control gate, which is positioned level with said channel, allowing a current to flow through said channel between the source and drain along an x-axis, said channel including: a first edge of separation with said source; and a second edge of separation with said drain; said channel being compressively or tensilely strained, characterized in that said channel includes a localized perforation or a set of localized perforations along at least said first and/or second edge of said channel so as to also create at least one shear strain in said channel. The invention also relates to a process for fabricating said transistor.

Abstract: A memory cell includes a curved gate channel transistor, a buried bit line, a word line and a capacitor. The curved gate channel transistor has a first doped region located in a substrate, a second doped region and a third doped region located on the substrate, wherein the second doped region is directly on the first doped region and the third doped region is right next to the second doped region, thereby constituting a curved gate channel. The buried bit line is located below the first doped region. The word line covers the second doped region. The capacitor is located above the curved gate channel transistor and in electrical contact with the third doped region. The present invention also provides a memory cell having a vertical gate channel transistor, and the vertical gate channel has current flowing downward.

Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.