Patents Examined by Albrecht
  • Magnetic memory device
    Patent number: 10923532
    Abstract: According to one embodiment, a magnetic memory device includes a semiconductor substrate, a first lower area provided on the semiconductor substrate, and including a plurality of magnetoresistive effect elements, a second lower area provided on the semiconductor substrate, and being adjacent to the first lower area, a first upper area provided above the first lower area, and including a first material film formed of an insulating material or a semiconductor material, and a second upper area provided above the second lower area, being adjacent to the first upper area, and including a second material film formed of an insulating material different from a material of the first material film.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: February 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akiyuki Murayama
  • Display device
    Patent number: 10886308
    Abstract: A display device includes a flexible substrate, a plurality of thin film transistors (TFTs), a first electrode arranged between a channel of one of the plurality of TFTs and the flexible substrate, at least one inorganic insulating film arranged between one of the plurality of TFTs and the first electrode, a second electrode arranged on the opposite side to the side where one of the plurality of TFTs is arranged with respect to the first electrode, and an organic insulating film arranged between the first electrode and the second electrode.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: January 5, 2021
    Assignee: Japan Display Inc.
    Inventors: Chunche Ma, Hajime Akimoto
  • Ultraviolet light-emitting element
    Patent number: 10879423
    Abstract: An ultraviolet light-emitting element includes: a multilayer stack in which an n-type AlGaN layer, a light-emitting layer, a first p-type AlGaN layer, and a second p-type AlGaN layer are arranged in this order; a negative electrode; and a positive electrode. The first p-type AlGaN layer has a larger Al composition ratio than first AlGaN layers serving as well layers. The second p-type AlGaN layer has a larger Al composition ratio than the first AlGaN layers. The first p-type AlGaN layer and the second p-type AlGaN layer both contain Mg. The second p-type AlGaN layer has a higher maximum Mg concentration than the first p-type AlGaN layer. The second p-type AlGaN layer includes a region where an Mg concentration increases in a thickness direction thereof as a distance from the first p-type AlGaN layer increases in the thickness direction.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: December 29, 2020
    Assignees: PANASONIC CORPORATION, RIKEN
    Inventors: Takayoshi Takano, Takuya Mino, Jun Sakai, Norimichi Noguchi, Hideki Hirayama
  • FinFET with etch-selective spacer and self-aligned contact capping layer
    Patent number: 10879180
    Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. An upper portion of the isolation architecture is removed and replaced with a high-k, etch-selective spacer layer adapted to resist degradation during an etch to open the source/drain contact locations. The high-k spacer layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate and overlapping a sidewall of the isolation layer, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: December 29, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Guowei Xu, Scott Beasor, Ruilong Xie
  • Using aluminum as etch stop layer
    Patent number: 10873023
    Abstract: A two-terminal resistive switching device (TTRSD) such as a non-volatile two-terminal memory device or a volatile two-terminal selector device can be formed according to a manufacturing process. The process can include forming an etch stop layer that is made of aluminum and can include forming a buffer layer below the etch stop layer and/or between the etch stop layer and a top electrode of the TTRSD.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: December 22, 2020
    Assignee: Crossbar, Inc.
    Inventors: Sundar Narayanan, Natividad Vasquez, Zhen Gu, Yunyu Wang
  • Magnetic tunnel junction integration without patterning process
    Patent number: 10868238
    Abstract: Certain aspects of the present disclosure provide techniques for fabricating an integrated circuit with a magnetic tunnel junction (MTJ) without a patterning process for the MTJ. An example method generally includes depositing a first diffusion barrier layer above an oxide layer having a conductive pillar therein, forming a first trench in the first diffusion barrier layer above the conductive pillar, depositing a first electrode in the first trench such that the first electrode is coupled to the conductive pillar, removing the oxide layer and the first diffusion barrier layer to expose the conductive pillar and the first electrode, and depositing an MTJ above the first electrode according to a shape of the first electrode.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 15, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Xia Li, Wei-Chuan Chen, Seung Hyuk Kang
  • Air spacers in transistors and methods forming same
    Patent number: 10861953
    Abstract: A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lun Chen, Chao-Hsien Huang, Li-Te Lin, Chun-Hsiung Lin
  • Micromechanical device having a decoupled micromechanical structure
    Patent number: 10843917
    Abstract: A micromechanical device having a substrate wafer, a functional layer situated above it which has a mobile micromechanical structure, and a cap situated on top thereof, having a first cavity, which is formed at least by the substrate wafer and the cap and which includes the micromechanical structure. The micromechanical device has a fixed part and a mobile part, which are movably connected to each other with at least one spring element, and the first cavity is situated in the mobile part. Also described is a method for producing the micromechanical device.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: November 24, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Steffen Zunft, Bonsang Kim, Ando Feyh, Andrew Graham, Gary O'Brien, Michael Baus, Ralf Maier, Mariusz Koc
  • Reducing junction leakage and occurrence of dark current at a contact portion of a solid-state image device
    Patent number: 10833128
    Abstract: There is provided a solid-state imaging device including a semiconductor base element, an organic photoelectric conversion layer formed above the semiconductor base element, a contact hole formed in an insulating layer on the semiconductor base element, a conductive layer formed in the contact hole and electrically connecting a photoelectric conversion part which includes the organic photoelectric conversion layer with the semiconductor base element, and a contact portion which is formed by self-alignment with the conductive layer in the contact hole in the semiconductor base element, and connected to the conductive layer.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: November 10, 2020
    Assignee: SONY CORPORATION
    Inventors: Yuki Miyanami, Masashi Nakazawa
  • Crystalline oxide semiconductor film, crystalline oxide semiconductor device, and crystalline oxide semiconductor system
    Patent number: 10804362
    Abstract: In a first aspect of a present inventive subject matter, a crystalline oxide semiconductor film includes a crystalline oxide semiconductor that contains a corundum structure as a major component, a dopant, and an electron mobility that is 30 cm2/Vs or more.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 13, 2020
    Assignee: FLOSFIA INC.
    Inventors: Rie Tokuda, Masaya Oda, Toshimi Hitora
  • Method for manufacturing semiconductor device
    Patent number: 10777643
    Abstract: A semiconductor device includes: a semiconductor substrate; a buffer layer provided on the semiconductor substrate; a GaN channel layer provided on the buffer layer; an AlGaN electron travel layer provided on the GaN channel layer; a GaN cap layer provided on the AlGaN electron travel layer, having a nitrogen polarity, and on which a plurality of recesses are formed; and a gate electrode, a source electrode and a drain electrode provided in each of the plurality of recesses.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: September 15, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kohei Miki
  • SiC-MOSFET and method of manufacturing the same
    Patent number: 10770579
    Abstract: An n-type drift region, a p-type first body region and a p-type contact region are formed on an SiC substrate by epitaxial growth. An opening is formed within the contact region by etching such that the first body region is exposed through the opening, and a p-type second body region is formed on the first body region exposed through the opening by epitaxial growth. An n-type source region is formed by epitaxial growth, and an opening is formed within a part of the source region located on the contact region by etching such that the contact region is exposed through the opening. A trench is formed by etching such that the trench extends from the source region to the drift region through the opening of the contact region, and a gate insulating film and a gate electrode are formed within the trench.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 8, 2020
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Yasushi Urakami, Yukihiko Watanabe
  • Layered structure, semiconductor device including layered structure, and semiconductor system including semiconductor device
    Patent number: 10770553
    Abstract: In a first aspect of a present inventive subject matter, a layered structure includes a first semiconductor layer containing as a major component an ?-phase oxide semiconductor crystal; and a second semiconductor layer positioned on the first semiconductor layer and containing as a major component an oxide semiconductor crystal with a tetragonal crystal structure.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 8, 2020
    Assignee: FLOSFIA INC.
    Inventors: Tokiyoshi Matsuda, Takashi Shinohe, Shingo Yagyu, Takuto Igawa
  • Regulating interface layer formation for two-terminal memory
    Patent number: 10693062
    Abstract: Provision of fabrication, construction, and/or assembly of a two-terminal memory device is described herein. The two-terminal memory device can include an active region with a silicon bearing layer, an interface layer, and an active metal layer. The interface layer can be grown on the silicon bearing layer, and the growth of the interface layer can be regulated with N2O plasma.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: June 23, 2020
    Assignee: Crossbar, Inc.
    Inventors: Sundar Narayanan, Sung Hyun Jo, Liang Zhao
  • Display substrate, its manufacturing method, and display device
    Patent number: 10663820
    Abstract: A method for manufacturing a display substrate includes a step of forming a pattern of a barrier layer and a pattern of a first electrode. The step of forming the pattern of the barrier layer and the pattern of the first electrode includes: forming a barrier layer film and a first electrode film sequentially; and forming the pattern of the barrier layer and the pattern of the first electrode by a single patterning process.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: May 26, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xianxue Duan, Mingji Bai, Dezhi Xu, Zhixiang Zou
  • Organic light emitting diode display
    Patent number: 10665651
    Abstract: An organic light emitting diode display includes a plurality of first signal lines, a first insulating layer covering the first signal lines, a plurality of second signal lines on the first insulating layer and crossing the first signal lines, and a plurality of pixels connected to the first signal lines and the second signal lines. A groove in the first insulating layer is between adjacent ones of the pixels and a filling material in the groove.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: May 26, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Min-Sung Kim, Thanh Tien Nguyen, Ki Ju Im
  • Vertically integrated active matrix backplane
    Patent number: 10651252
    Abstract: A method of forming an active matrix pixel that includes forming a driver device including contact regions deposited using a low temperature deposition process on a first portion of an insulating substrate. An electrode of an organic light emitting diode is formed on a second portion of the insulating substrate. The electrode is in electrical communication to receive an output from the driver device. At least one passivation layer is formed over the driver device. A switching device comprising at least one amorphous semiconductor layer is formed on the at least one passivation layer over the driver device.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: May 12, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen M. Gates, Bahman Hekmatshoartabari, Ghavam G. Shahidi, Davood Shahrjerdi
  • High-voltage semiconductor device and method for manufacturing the same
    Patent number: 10629726
    Abstract: The present disclosure provides a high-voltage semiconductor device, including: a substrate; an epitaxial layer disposed over the substrate and having a first conductive type; a gate structure disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate structure respectively; and a stack structure disposed between the gate structure and the drain region, wherein the stack structure includes: a blocking layer; an insulating layer disposed over the blocking layer; and a conductive layer disposed over the insulating layer and electrically connected the source region or the gate structure. The present disclosure also provides a method for manufacturing the high-voltage semiconductor device.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 21, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chung-Ren Lao, Hsing-Chao Liu, Chu-Feng Chen, Wei-Chun Chou
  • Integrated LDMOS and VFET transistors
    Patent number: 10615159
    Abstract: Embodiments are directed to devices and methods for integrating laterally diffused metal oxide semiconductor (LDMOS) technology on vertical field effect transistor (VFET) technology, which enables VFET applications to be broadened to include power amplifiers. By providing a combined asymmetric underlapped drain, high current, low subthreshold slope and LDMOS lightly doped drain, high drain resistance and high drain voltage are enabled.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Fabrication of vertical fin field effect transistors having top air spacers and a self-aligned top junction
    Patent number: 10535652
    Abstract: A method of fabricating adjacent vertical fins with top source/drains having an air spacer and a self-aligned top junction, including, forming two or more vertical fins on a bottom source/drain, forming a top source/drain on each of the two or more vertical fins, wherein the top source/drains are formed to a size that leaves a gap between the adjacent vertical fins, and forming a source/drain liner on the top source/drains, where the source/drain liner occludes the gap between adjacent top source/drains to form a void space between adjacent vertical fins.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: January 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang