Abstract: A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface is prepared. A surface electrode is formed in contact with the first main surface of the silicon carbide substrate. An adhesive tape is adhered to the surface electrode so as to cover the surface electrode. The silicon carbide substrate is heated at a first pressure lower than atmospheric pressure, with the adhesive tape being adhered to the surface electrode. After the silicon carbide substrate is heated, the second main surface of the silicon carbide substrate is ground. After the second main surface is ground, the second main surface of the silicon carbide substrate is processed at a second pressure lower than atmospheric pressure, with the adhesive tape being adhered to the surface electrode.

Abstract: Methods of forming a passivation layer on a workpiece are disclosed. These methods utilize a SiC forming polymer to form the passivation layer. In addition, while the polymer is being heated to form SiC, a second result, such as annealing of the underlying workpiece, or firing of the metal contacts is achieved. For example, the workpiece may be implanted prior to coating it with the polymer. When the workpiece is heated, SiC is formed and the workpiece is annealed. In another embodiment, a workpiece is coating with the SiC forming polymer and metal pattern is applied to the polymer. The firing of workpiece causes the metal contacts to form and also forms SiC on the workpiece.

Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.

Abstract: A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The method includes substantially simultaneously forming a first opening and a second opening extending from the semiconductor layer to the conductive region; introducing an insulating material to the side walls of the first opening; at least partially filling the first opening with a semiconductor material to provide an ohmic contact trench; and at least partially filling the second opening with an insulating material to form a device isolation trench. Insulating regions, for example, shallow trench isolation (STI) regions, may be formed about the device isolation trench and the ohmic contact trench. Semiconductor structures are also provided.

Abstract: Methods of growing nitride semiconductor layers including forming nitride semiconductor dots on a substrate and growing a nitride semiconductor layer on the nitride semiconductor dots. The nitride semiconductor layer may be separated from the substrate to be used as a nitride semiconductor substrate.

Abstract: A dicing sheet includes a base, an intermediate layer on one face of the base, and an pressure sensitive adhesive layer provided on the intermediate layer and having the thickness of 8 to 30 ?m. The pressure sensitive adhesive layer includes a compound having an energy ray curable double bond in a molecule, and a storage elasticity G? at 23° C. of the pressure sensitive adhesive layer before curing is larger than 4 times of a storage elasticity at 23° C. of the intermediate layer. When the dicing sheet is laminated via the adhesive sheet on a wafer formed with a cylinder shape electrodes having a height of 15 ?m and a diameter of 15 ?m at a pitch of 40 ?m having 3 rows 3 columns in equal spacing, at a center of the electrode of the cylinder shape electrodes formed in 3 rows 3 columns, the pressure sensitive adhesive layer does not contact at a part of a height of 7.5 ?m or less of the electrode.

Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer including a first surface, a second surface opposite to the first surface, and a light emitting layer; a p-side electrode provided on the second surface of the semiconductor layer in a region including the light emitting layer; an n-side electrode provided on the second surface of the semiconductor layer in a region not including the light emitting layer; an insulating film being more flexible than the semiconductor layer, the insulating film provided on the second surface and a side surface of the semiconductor layer, and the insulating film having a first opening reaching the p-side electrode and a second opening reaching the n-side electrode; a p-side interconnection layer provided on the insulating film and connected to the p-side electrode; and an n-side interconnection layer provided on the insulating film and connected to the n-side electrode.

Abstract: A suspension for protecting a semiconductor material includes a polymeric matrix as carrier medium, inorganic particles, and at least one of an absorber dye or a plasticizer.

Abstract: A power supply system has a QFN leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound.

Abstract: There is provided an electroless plating apparatus which, despite using a high-productivity batch processing method, can reduce the amount of a liquid chemical brought out of a processing tank, thereby reducing the cleaning time in a cleaning step, and can perform flushing easily and quickly. The electroless plating apparatus includes a pre-plating treatment module including a pre-plating treatment tank, a plating module, and an inter-module substrate transport device. The pre-plating treatment tank is provided with a pre-plating treatment solution circulation line having a temperature control function for a pre-plating treatment solution. The plating tank is provided with a plating solution circulation line having a filter and a temperature control function for a plating solution. The plating solution circulation line is connected to a flushing line for flushing the interior of the plating solution circulation line and the interior of the plating tank.

Abstract: A fabrication method for dicing semiconductor wafers using laser cutting techniques, which can effectively prevent the devices on semiconductor die units from the phenomenon of etching undercut caused by the sequential steps after laser cutting, comprises following steps: covering the wafer surface with a protection layer; dicing the wafer by laser and separating the die units from each other; removing the laser cutting residues on the devices on the die units via wet etching by an acidic water solution; removing the protection layer by a non-acidic water solution and cleaning the devices on the die units. The selection of materials for the protection layer must consider the following factors: where (1) the materials for the protection layer must have relatively good properties for adhering and covering on the wafer; (2) the materials for the protection layer must be corrosion-resistant to the acidic water solution for etching residues.

Abstract: An optoelectronic device, comprising: a first organic functional layer structure; a second organic functional layer structure; and a charge generating layer structure between the first organic functional layer structure and the second organic functional layer structure, wherein the charge generating layer structure comprises: a first electron-conducting charge generating layer; wherein the first electron-conducting charge generating layer comprises or is formed from an intrinsically electron-conducting substance; a second electron-conducting charge generating layer; and an interlayer between first electron-conducting charge generating layer; and second electron-conducting charge generating layer; and wherein the interlayer comprises at least one phthalocyanine derivative.

Abstract: A method for fabricating the OLED including a color conversion layer using roll-to-roll processing is provided. To elaborate, the method for fabricating an OLED comprising: bonding an OLED and an inorganic phosphor to each other through roll-to-roll processing is provided, wherein the inorganic phosphor is provided as a color conversion layer.

Abstract: Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.

Abstract: Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Abstract: A silicon carbide semiconductor substrate is made of a silicon carbide single crystal and is formed with a stamp on at least a surface as an identification indication formed of a crystal defect. When a silicon carbide single crystal is allowed to grow using the silicon carbide semiconductor substrate as a seed crystal, the stamp can be propagated to the silicon carbide single crystal as a crystal defect. When silicon carbide semiconductor substrates are manufactured using the silicon carbide single crystal, the stamp has already been formed on each of the silicon carbide semiconductor substrates.

Abstract: A substrate and a delamination film are separated by a physical means, or a mechanical means in a state where a metal film formed over a substrate, and a delamination layer comprising an oxide film including the metal and a film comprising silicon, which is formed over the metal film, are provided. Specifically, a TFT obtained by forming an oxide layer including the metal over a metal film; crystallizing the oxide layer by heat treatment; and performing delamination in a layer of the oxide layer or at both of the interface of the oxide layer is formed.

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

Abstract: A semiconductor light-emitting diode, including: an n-GaN layer, a quantum well layer, an electron blocking layer, and a p-GaN layer, which are sequentially stacked on a substrate. The electron blocking layer includes at least one first AlGaN layer and at least one second AlGaN layer. The first AlGaN layer and the second AlGaN layer are alternately stacked. The adjacent first and second AlGaN layers have different Al component.

Abstract: A method including forming a penta-layer hardmask above a substrate, the penta-layer hardmask comprising a first hardmask layer above a second hardmask layer; forming a trench pattern in the first hardmask layer; transferring a first via bar pattern from a first photo-resist layer above the penta-layer hardmask into the second hardmask layer resulting in a first via pattern, the first via pattern in the second hardmask layer overlapping the trench pattern and being self-aligned on two sides by the trench pattern in the first hardmask layer; and transferring the first via pattern from the second hardmask layer into the substrate resulting in a self-aligned via opening, the self-aligned via opening being self-aligned on all sides by the first via pattern in the second hardmask layer.