Patents Examined by Alexander Ghyka
  • Hard mask as contact etch stop layer in image sensors
    Patent number: 9484373
    Abstract: An image sensor includes a semiconductor material with a photodiode disposed in the semiconductor material, and a transfer gate disposed adjacent to an edge of the photodiode. A dielectric layer is also disposed between the semiconductor material and the transfer gate. A hard mask is disposed in an encapsulation layer and lateral bounds of the hard mask are coextensive with lateral bounds of the transfer gate. A first contact trench extends through the encapsulation layer and through the dielectric layer and contacts the semiconductor material. A second contact trench extends through the encapsulation layer and through the hard mask and contacts the transfer gate.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: November 1, 2016
    Assignee: OmniVision Technologies, Inc.
    Inventors: Gang Chen, Yuanwei Zheng, Duli Mao, Dyson Tai
  • Optoelectronic semiconductor component
    Patent number: 9484508
    Abstract: The invention relates to an optoelectronic semiconductor component, which has a carrier element (1), on which an optoelectronic semiconductor chip (2) having at least one active layer is arranged, wherein the active layer is designed to emit or receive light during operation and wherein the semiconductor chip (2) is covered with a protective layer (3) that contains poly-para-xylenes.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 1, 2016
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Georg Dirscherl, Walter Wegleiter, Caroline Cassignol, Karl Weidner
  • Wafer to wafer structure and method of fabricating the same
    Patent number: 9478496
    Abstract: A wafer to wafer structure includes a first wafer, a second wafer. A first bonding layer and a second bonding layer are disposed between the first wafer and the second wafer. A plurality of first interconnects are disposed within the he first bonding layer. A plurality of second interconnects are disposed within the second bonding layer. An interface is disposed between the first bonding layer and the second bonding layer. At least a through silicon via penetrates the first wafer, the first bonding layer and the interface to enter the second bonding layer. The through silicon via contacts one of the first interconnects and one of the second interconnects.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: October 25, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ming-Tse Lin
  • Methods of cross-coupling line segments on a wafer
    Patent number: 9472455
    Abstract: A method is provided for fabricating cross-coupled line segments on a wafer for use, for instance, in fabricating cross-coupled gates of two or more transistors. The fabricating includes: patterning a first line segment with a first side projection using a first mask; and patterning a second line segment with a second side projection using a second mask. The second line segment is offset from the first line segment, and the patterned second side projection overlies the patterned first side projection, and facilitates defining a cross-stitch segment connecting the first and second line segments. The method further includes selectively cutting the first and second line segments in defining the cross-coupled line segments from the first and second line segments and the cross-stitch segment.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: October 18, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jason E. Stephens, Lei Yuan, Lixia Lei, David Pritchard, Tuhin Guha Neogi
  • Semiconductor structure having a dual-gate non-volatile memory device and methods for making same
    Patent number: 9466608
    Abstract: A method for making a semiconductor structure includes forming an oxide layer onto non-volatile memory, high, and low voltage device regions of a substrate and forming a first gate material layer over the oxide layer. The first gate material layer is patterned to form a set of memory device select gates in the non-volatile memory device region and a set of gates in the high voltage device region. The patterning is performed while maintaining the oxide and first gate material layers over the low voltage device region. The method also includes forming a second gate material layer over the structure and forming a non-volatile storage layer between the set of select gates and the second gate material layer, from which a set of memory device control gates is patterned. Thereafter, the first gate material layer is patterned to form a set of gates in the low voltage device region.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: October 11, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Weize Chen, Richard J De Souza, Patrice M Parris
  • Optoelectronic device and method for producing an optoelectronic device
    Patent number: 9466759
    Abstract: A method is provided for producing an optoelectronic device, comprising the steps of providing a substrate, applying a nucleation layer on a surface of the substrate, applying and patterning a mask layer on the nucleation layer, growing a nitride semiconductor in a first growth step, wherein webs are laid which form a lateral lattice, wherein the webs have trapezoidal cross-sectional areas in places in the direction of growth, and laterally overgrowing the webs with a nitride semiconductor in a second growth step, to close spaces between the webs.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: October 11, 2016
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Joachim Hertkorn, Jan-Philipp Ahl, Lorenzo Zini, Matthias Peter, Tobias Meyer, Alexander Frey
  • Semiconductor device and method of fabricating the same
    Patent number: 9466727
    Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a metal-oxide-semiconductor (MOS) transistor, a plug, a hydrogen blocking layer and an oxide semiconductor (OS) structure. The MOS transistor is disposed on the substrate, and the plug is disposed on the MOS transistor to electrically connect thereto. The hydrogen blocking layer is disposed only on sidewalls of the plug, wherein the hydrogen blocking layer includes a high-k dielectric layer. The OS structure is disposed on the substrate, wherein the OS structure includes an oxide semiconductor layer.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Fu Hsu, Chun-Yuan Wu
  • LDMOS device with graded body doping
    Patent number: 9461046
    Abstract: A laterally diffused MOS (LDMOS) device includes a substrate having a p-epi layer thereon. A p-body region is in the p-epi layer. An ndrift (NDRIFT) region is within the p-body region providing a drain extension region, and a gate dielectric layer is formed over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region, and a patterned gate electrode on the gate dielectric. A DWELL region is within the p-body region, sidewall spacers are on sidewalls of the gate electrode, a source region is within the DWELL region, and a drain region is within the NDRIFT region. The p-body region includes a portion being at least one 0.5 ?m wide that has a net p-type doping level above a doping level of the p-epi layer and a net p-type doping profile gradient of at least 5/?m.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 4, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, James Robert Todd
  • Semiconductor device having structure with fractional dimension of the minimum dimension of a lithography system
    Patent number: 9460924
    Abstract: A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: October 4, 2016
    Assignee: Globalfoundries, Inc.
    Inventors: Witold P. Maszara, Qi Xiang
  • Surface poisoning using ALD for high selectivity deposition of high aspect ratio features
    Patent number: 9460932
    Abstract: Methods of selectively depositing a feature onto a substrate surface while maintaining substantially straight sidewalls on the feature. A portion of the feature is grown and then covered with a protective film. The protective film is removed from the top of the feature, leaving some of the film on the sides of the feature and the process is repeated to grow a feature of desired thickness.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: October 4, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Paul F. Ma, Jiang Lu, Guodan Wei
  • Differential temperature sensor
    Patent number: 9461231
    Abstract: This sensor (1) includes an assembly of thermoelectric layers, a support member (2) including at least one first and one second metallic connector pins (30, 31), first and second metal connectors arranged to electrically connect the support member (2) respectively to a first connection pad and a second connection pad, an external package (8) including a first surface (8a) and a second opposite surface (8b) intended to be respectively connected to a hot source and to a cold source, a first via (80) connecting the first surface (8a) to each first connector pin (30), a second via (81) connecting the second surface (8b) to each second connector pin (31), and the support member (2) includes thermal conductors between the connector pins (30, 31) and the metal connectors.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 4, 2016
    Assignees: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, HOTBLOCK ONBOARD
    Inventors: Guillaume Savelli, Joël Dufourcq
  • Mask set and method for fabricating semiconductor device by using the same
    Patent number: 9455202
    Abstract: A mask set includes a first mask and a second mask. The first mask includes geometric patterns. The second mask includes at least a strip-shaped pattern with a first edge and a second edge opposite to the first edge. The strip-shaped pattern has a centerline along a long axis of the strip-shaped pattern. The first edge includes inwardly displaced segments shifting towards the centerline and each of the inwardly displaced segments overlaps each of the geometric patterns.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: September 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Chi Lee, Yu-Lin Wang, Chung-Yuan Lee
  • IC having failsafe fuse on field dielectric
    Patent number: 9455222
    Abstract: A fuse circuit includes a substrate, a top semiconductor layer doped a first conductivity type having a well doped a second conductivity type formed therein including a well contact. A field dielectric layer (FOX) is on the semiconductor layer. A fuse is on the FOX within the well including a fuse body including electrically conductive material having a first and second fuse contact. A transistor is formed in the semiconductor layer including a control terminal (CT) with CT contact, a first terminal (FT) with FT contact, and a second terminal (ST) with a ST contact. A coupling path is between the CT contact and well contact, a first resistor is coupled between the FT contact and CT contact, and a coupling path is between the ST contact and the first fuse contact.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: September 27, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hideaki Kawahara, Hong Yang, Eugen Pompiliu Mindricelu, Robert Graham Shaw
  • Stacked semiconductor chips packaging
    Patent number: 9449907
    Abstract: Various methods and apparatus for joining stacked substrates to a circuit board are disclosed. In one aspect, a method of manufacturing is provided that includes coupling plural substrates to form a stack. At least one of the plural substrates is a semiconductor chip. Plural conductive vias are formed in a first of the plural substrates. Each of the plural conductive vias includes a first end positioned in the first substrate and a second end projecting out of the first substrate.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: September 20, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lei Fu, Frank Gottfried Kuechenmeister, Michael Zhuoying Su
  • Method of making damascene select gate in memory device
    Patent number: 9443867
    Abstract: A method of fabricating a memory device includes forming a mask over a top surface of a stack of alternating insulating material layers and control gate electrodes located over a substrate, wherein the stack has a memory opening extending vertically through the stack, a semiconductor channel extends vertically in the memory opening, and a memory film is located in the memory opening between the semiconductor channel and the plurality of control gate electrodes, and the mask covers a first portion of an upper insulating layer of the stack and exposes a second portion of the upper insulating layer adjacent to the memory opening, etching the upper insulating layer through the mask to provide a recess in the second portion of the upper insulating layer, and forming a conductive material within the recess to provide a select gate electrode adjacent to the semiconductor channel in the memory opening.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: September 13, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Shingo Ohsaki
  • Multi-step system and method for curing a dielectric film
    Patent number: 9443725
    Abstract: A multi-step system and method for curing a dielectric film in which the system includes a drying system configured to reduce the amount of contaminants, such as moisture, in the dielectric film. The system further includes a curing system coupled to the drying system, and configured to treat the dielectric film with ultraviolet (UV) radiation and infrared (IR) radiation in order to cure the dielectric film.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: September 13, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Junjun Liu, Eric M. Lee, Dorel I. Toma
  • Method of forming a semiconductor die
    Patent number: 9437493
    Abstract: In one embodiment, semiconductor die having non-rectangular shapes and die having various different shapes are formed and singulated from a semiconductor wafer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: September 6, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gordon M. Grivna, Michael J. Seddon
  • Method for making a semiconductor device with sidewall spacers for confining epitaxial growth
    Patent number: 9431540
    Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: August 30, 2016
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES Inc., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Liu, Ruilong Xie, Xiuyu Cai, Chun-chen Yeh
  • Integrated circuit devices including contacts and methods of forming the same
    Patent number: 9431492
    Abstract: Integrated circuit devices including contacts and methods of forming the same are provided. The devices may include a fin on a substrate, a gate structure on the fin and a source/drain region in the fin at a side of the gate structure. The devices may further include a contact plug covering an uppermost surface of the source/drain region and a sidewall of the gate structure. The contact plug may include an inner portion including a first material and an outer portion including a second material different from the first material. The outer portion may at least partially cover a sidewall of the inner portion, and a portion of the outer portion may be disposed between the sidewall of the gate structure and the sidewall of the inner portion.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jorge A. Kittl, Dharmendar Reddy Palle, Mark S. Rodder
  • Electrostatic discharge devices and methods of manufacture
    Patent number: 9425184
    Abstract: Electrostatic discharge (ESD) devices and methods of manufacture are provided. The method includes forming a plurality of fin structures and a mesa structure from semiconductor material. The method further includes forming an epitaxial material with doped regions on the mesa structure and forming gate material over at least the plurality of fin structures. The method further includes planarizing at least the gate material such that the gate material and the epitaxial material are of a same height. The method further includes forming contacts in electrical connection with respective ones of the doped regions of the epitaxial material.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: August 23, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huiming Bu, Junjun Li, Theodorus E. Standaert, Tenko Yamashita