Abstract: The present invention provides a composition for forming a coating type BPSG film, which comprises: one or more structures comprising a silicic acid represented by the following general formula (1) as a skeletal structure, one or more structures comprising a phosphoric acid represented by the following general formula (2) as a skeletal structure and one or more structures comprising a boric acid represented by the following general formula (3) as a skeletal structure. There can be provided a composition for forming a coating type BPSG film which is excellent in adhesiveness in fine pattern, can be easily wet etched by a peeling solution which does not cause any damage to the semiconductor apparatus substrate, the coating type organic film or the CVD film mainly comprising carbon which are necessary in the patterning process, and can suppress generation of particles by forming it in the coating process.

Abstract: A first semiconductor structure including a first bonding oxide layer having a metal resistor structure embedded therein and a second semiconductor structure including a second bonding oxide layer having a metallic bonding structure embedded therein are provided. A nitride surface treatment process is performed to provide a nitrided surface layer to each structure. Each nitrided surface layer includes nitridized oxide regions located in an upper portion of the bonding oxide layer and nitridized metallic regions located in an upper portion of either the metal resistor structure or the metallic bonding structure. The nitrogen within the nitridized metallic region located in the upper portion of the metallic bonding structure is then selectively removed to restore the upper portion of the metallic bonding structure to its original composition. Bonding is then performed to form a dielectric bonding interface and a metallic bonding interface between.

Abstract: A photoconductor includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, a first electrode connected to a first lateral side of the first semiconductor layer and the second semiconductor layer, and a second electrode connected to a second lateral side of the first semiconductor layer and the second semiconductor layer, where the first semiconductor layer and the second semiconductor layer form a type II junction or a quasi-type-II junction.

Abstract: The present invention provides a peeling off method without giving damage to the peeled off layer, and aims at being capable of peeling off not only a peeled off layer having a small area but also a peeled off layer having a large area over the entire surface at excellent yield ratio. The metal layer or nitride layer 11 is provided on the substrate, and further, the oxide layer 12 being contact with the foregoing metal layer or nitride layer 11 is provided, and furthermore, if the lamination film formation or the heat processing of 500° C. or more in temperature is carried out, it can be easily and clearly separated in the layer or on the interface with the oxide layer 12 by the physical means.

Abstract: Embodiments of the present disclosure provide methods for forming stair-like structures in manufacturing three dimensional (3D) stacking of semiconductor chips. In one example, a method includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, performing an etching process to etch a portion of the film stack exposed by the trimmed patterned photoresist layer, directing an optical signal to a surface of the trimmed patterned photoresist layer continuously during the trimming and the etching process, collecting a return reflected optical signal reflected from the trimmed patterned photoresist layer, determining a change of reflected intensify of the return reflected optical signal as collected; and calculating a photoresist thickness loss based on the change of the reflected intensity.

Abstract: The present invention provides a thin film transistor substrate and a display device that prevent peeling. The thin film transistor substrate includes: an insulating substrate; a thin film transistor; a first inorganic insulating layer; an organic insulating layer stacked on the first inorganic insulating layer; and a second inorganic insulating layer stacked on the organic insulating layer. The organic insulating layer includes a side covered with the second inorganic insulating layer. The first inorganic insulating layer may contain silicon oxide. The organic insulating layer may contain photosensitive resin. The second inorganic insulating layer may contain silicon nitride.

Abstract: An optical sensor module is disclosed. The optical sensor module can include a housing comprising an air cavity. An optical emitter die can be disposed in the air cavity of the housing. A top surface of the optical emitter die can face a first side of the housing, the optical emitter die configured to emit light towards the first side of the housing. An optical sensor die can be disposed in the air cavity of the housing adjacent the optical emitter die. The optical sensor die can be spaced from the optical emitter die by a lateral distance. A top surface of the optical sensor die can face the first side of the housing. There may be no septum between the optical sensor die and the optical emitter die that optically separates the optical sensor die and the optical emitter die.

Abstract: An optoelectronic semiconductor component and a method for making an optoelectronic semiconductor component are disclosed. In an embodiment the component includes a carrier including at least one conversion-medium body and a potting body, the potting body surrounding the conversion-medium body at least in places, as seen in plan view, electrical contact structures fitted at least indirectly to the carrier and a plurality of optoelectronic semiconductor chips fitted to a main face of the carrier, the optoelectronic semiconductor chips configured to generate radiation, wherein the conversion-medium body is shaped as a plate, wherein the semiconductor chips are directly mechanically connected to the conversion-medium body, and wherein the conversion-medium body is free of cutouts for the electrical contact structures and is not penetrated by the electrical contact structure.

Abstract: This application relates to MEMS devices, especially MEMS capacitive transducers and to processes for forming such MEMS transducer that provide increased robustness and resilience to acoustic shock. The application describes a MEMS transducer having a flexible membrane (101) supported relative to a first surface of a substrate (105) which has one or more cavities therein, e.g. to provide an acoustic volume. A stop structure (401, 402) is positioned so as to be contactable by the membrane when deflected so as to limit the amount of deflection of the membrane. The stop structure defines one or more openings to the one or more substrate cavities and comprises at least one narrow support element (401, 402) within or between said one or more openings. The stop structure thus limits the amount of membrane deflection, thus reducing the stress experienced at the edges and prevents the membrane from contacting a sharp edge of a substrate cavity.

Abstract: A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.

Abstract: A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-mirror) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation).

Abstract: A preparation method of a graphene nanoribbon on h-BN, comprising: 1) forming a h-BN groove template with a nano ribbon-shaped groove structure on the h-BN by adopting a metal catalysis etching method; 2) growing a graphene nanoribbon in the h-BN groove template by adopting a chemical vapor deposition method. In the present invention, a CVD method is adopted to directly prepare a morphology controllable graphene nanoribbon on the h-BN, which helps to solve the long-term critical problem that the graphene is difficult to nucleate and grow on an insulating substrate, and to avoid the series of problems introduced by the complicated processes of the transferring of the graphene and the subsequent clipping manufacturing for a nanoribbon and the like.

Abstract: A method of forming perovskite thin films with micron-sized perovskite grains is provided. A layer of PbX2 in a solution containing a metal ion additive is applied to a structure. The structure with the PbX2 layer is annealed a first time. The PbX2 is exposed to CH3NH3X in a solvent. The structure with the exposed PbX2 layer is annealed a second time resulting in a CH3NH3PbX3 layer. X is selected from a group consisting of Cl, Br, I, CN, and SCN.

Abstract: A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; where the second layer includes at least one through layer via to provide connection between at least one of the second transistors and at least one of the first transistors, where the at least one through layer via has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; and a second set of external connections overlying the second layer to connect the device to external devices.

Abstract: A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the luminous flux independently of the temperature. The embedded layer is interleaved between a first treatment layer and a second treatment layer. The first treatment layer has a coefficient of absorption of luminous flux that is low at ambient temperature and rises as the temperature rises. The luminous flux may be applied in several places of a surface of the first layer to heat regions of the embedded layer and generate a propagating thermal front in the first layer opposite the heated regions of the embedded layer, which generate constraints within the second layer.

Abstract: A method for the formation of a MIM capacitor on a substrate is described. Initially, a target comprising a metal is sputtered in the presence of nitrogen to form at least a portion of a bottom electrode. Next, the target is further sputtered in the presence of oxygen to form at least a part of an insulator. Finally, the target is even further sputtered in the presence of nitrogen to form a portion of a top electrode. The insulator is sandwiched between the bottom electrode and the top electrode. The formation of the bottom electrode, the insulator, and the top electrode is performed in a sputter deposition chamber without removing the substrate therefrom.

Abstract: A method of image sensor fabrication includes forming a layer of dielectric material, a layer of gate material, and a layer of hard mask material. The layer of dielectric material is disposed between the layer of gate material and a semiconductor material, and the layer of gate material is disposed between the layer of hard mask material and the layer of dielectric material. The method also includes etching the layer of hard mask material and layer of gate material, and etching forms a transfer gate from the layer of gate material. An encapsulation material is deposited proximate to a surface of the semiconductor material. Trenches are etched in the encapsulation material. A first trench extends through the encapsulation material and the layer of dielectric material, and a second trench extends through the encapsulation material and the layer of hard mask material.

Abstract: Placing a conductive member between a plasma chamber in a remote plasma reactor and a substrate to shield the substrate from irradiation of undesirable electromagnetic radiation, ions or electrons. The conductive member blocks the electromagnetic radiation, neutralizes ions and absorbs the electrons. Radicals generated in the plasma chambers flows to the substrate despite the placement of the conductive member. In this way, the substrate is exposed to the radicals whereas damages to the substrate due to electromagnetic radiations, ions or electrons are reduced or removed.

Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.

Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes: respectively forming a first layer and a second layer at the top of a protruding portion and at the bottom of a depressed portion of a treatment target having protrusions/depressions in such a manner that sidewalls of the protruding portion is exposed, supplying a treatment liquid to the treatment target having the first layer and the second layer, bringing a catalyst into contact with or closer to the first layer and thereby increasing the dissolution rate of the first layer in dissolving into the treatment liquid and dissolving the first layer into the treatment liquid, and sequentially dissolving the protruding portion and the second layer into the treatment liquid after the dissolution of the first layer.