Patents Examined by Alexander O. Williams
  • Patent number: 10566301
    Abstract: A reconfigured semiconductor logic device includes a semiconductor logic device comprising a plurality of input/output (I/O) pads formed on an active surface thereof and a redistribution layer. The redistribution layer comprises an insulating layer formed atop the active surface of the semiconductor logic device such that the insulating layer does not extend beyond an outer perimeter of the active surface and a patterned conductive wiring layer positioned above the insulating layer. The patterned conductive wiring layer includes a plurality of terminal buses formed on a top surface of the insulating layer. Each terminal bus of the plurality of terminal buses is electrically coupled to multiple I/O pads of the plurality of I/O pads through vias formed in the insulating layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: February 18, 2020
    Assignee: General Electric Company
    Inventors: Raymond Albert Fillion, Kaustubh Ravindra Nagarkar
  • Patent number: 10566406
    Abstract: An organic light emitting diode display includes a plurality of pixels. At least one pixel is connected to a scan line receive a scan signal, a data line to receive a data signal, and voltage line to receive a driving voltage. The at least one pixel includes a switching transistor including a switching drain electrode to output the data voltage, a driving transistor including a driving source electrode connected to the switching drain electrode, and an organic light emitting diode connected to a driving drain electrode of the driving transistor. The driving source electrode is separated from the data line.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Mi Hae Kim, Min Ho Ko, Seung Woo Sung, Ki Myeong Eom, Jin Jeon
  • Patent number: 10566306
    Abstract: The disclosure provides a wiring structure of a glass substrate used between a demultiplexer MUX and an integrated circuit IC. The siring structure includes a plurality of connecting lines, two ends of each connecting line are connected to the MUX and the IC, and a predetermined spacing is reserved between any two adjacent connecting lines. Wherein one or more conductive convex teeth are provided on at least one connecting line, and a predetermined distance is reserved between each convex tooth on any one of the connecting lines and an adjacent connecting line thereof or each convex tooth on the adjacent connecting line. The disclosure also provides a glass substrate and a display device. Performing the disclosure may reduce the resistance of the wiring in the present limited wiring space and improve the charging effect of the glass substrate.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 18, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Huanda Wu
  • Patent number: 10566366
    Abstract: A photodetection device including a diode array and a method for production thereof. In the device, each diode of the array includes an absorption region having a first bandgap energy and a collection region having a first doping type, and adjacent diodes in a network are separated by a trench including sides and a bottom. The bottom and sides of the trench form a stabilization layer having a second doping type, opposite the first doping type, and a bandgap energy greater than the first bandgap energy of the absorption regions.
    Type: Grant
    Filed: November 25, 2016
    Date of Patent: February 18, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Johan Rothman, Florent Rochette
  • Patent number: 10566261
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 10553742
    Abstract: A substrate has a front surface and a back surface opposite from the front surface. An n-type layer, a multiplication layer, a p-type electric field control layer, a light absorption layer, and a window layer are layered in order on the front surface. A p-type region is provided in part of the window layer. An anode electrode is provided on the p-type region and connected to the p-type region. An anode pad and a cathode pad are provided on the back surface. First and second connecting holes penetrates the substrate. A third connecting hole penetrates from the window layer to the n-type layer. The cathode pad is electrically connected to the n-type layer via the first connecting hole. The anode pad is electrically connected to the anode electrode via the second and third connecting holes. A light-receiving region is provided on the back surface.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: February 4, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Ryota Takemura, Nobuo Ohata, Yoshifumi Sasahata, Kazuki Yamaji
  • Patent number: 10553532
    Abstract: Embodiments of the invention include interconnect structures with overhead vias and through vias that are self-aligned with interconnect lines and methods of forming such structures. In an embodiment, an interconnect structure is formed in an interlayer dielectric (ILD). One or more first interconnect lines may be formed in the ILD. The interconnect structure may also include one or more second interconnect lines in the ILD that arranged in an alternating pattern with the first interconnect lines. Top surfaces of each of the first and second interconnect lines may be recessed below a top surface of the ILD. The interconnect structure may include a self-aligned overhead via formed over one or more of the first interconnect lines or over one or more of the second interconnect lines. In an embodiment, a top surface of the self-aligned overhead via is substantially coplanar with a top surface of the ILD.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Richard E. Schenker, Manish Chandhok, Robert L. Bristol, Mauro J. Kobrinsky, Kevin Lin
  • Patent number: 10553615
    Abstract: Provided is an array substrate, a photomask, and a display device. The array substrate includes a substrate, a common electrode layer on which a plurality of first via holes are provided at predetermined positions, a passivation layer having a plurality of second via holes disposed concentrically with the first via holes, and a pixel electrode layer having a plurality of pixel electrodes. Areas of the first via holes are configured to gradually decrease in the direction from an output proximal end to an output distal end of a gate line.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 4, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventor: Kaixiang Zhao
  • Patent number: 10546957
    Abstract: A semiconductor device includes a semiconductor wafer having one or more suspended nanosheet extending between first and second source/drain regions. A gate structure wraps around the nanosheet stack to define a channel region located between the source/drain regions. The semiconductor device further includes a first all-around source/drain contact formed in the first source/drain region and a second all-around source/drain contact formed in the second source/drain region. The first and second all-around source/drain contacts each include a source/drain epitaxy structure and an electrically conductive external portion that encapsulates the source/drain epitaxy structure.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Xu, Chun Wing Yeung, Chen Zhang
  • Patent number: 10546825
    Abstract: An antenna semiconductor package device includes: (1) a waveguide cavity having a radiation opening; and (2) a first directing element outside of the waveguide cavity and separated from the waveguide cavity by a first gap.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: January 28, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-En Hsu, Huei-Shyong Cho, Shih-Wen Lu
  • Patent number: 10535643
    Abstract: A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated circuit (PMIC).
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: January 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun Tae Lee, Han Kim, Hyung Joon Kim
  • Patent number: 10535596
    Abstract: Various embodiments of a feedthrough assembly and methods of forming such assemblies are disclosed. In one or more embodiments, the feedthrough assembly can include a non-conductive substrate and a feedthrough. The feedthrough can include a via from an outer surface to an inner surface of the non-conductive substrate, a conductive material disposed in the via, and an external contact disposed over the via on the outer surface of the non-conductive substrate. The external contact can be electrically coupled to the conductive material disposed in the via. And the external contact can be hermetically sealed to the outer surface of the non-conductive substrate by a bond surrounding the via. In one or more embodiments, the bond can be a laser bond.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: January 14, 2020
    Assignee: Medtronic, Inc.
    Inventors: David A. Ruben, Michael S. Sandlin
  • Patent number: 10535599
    Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: January 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kwang-Soo Kim
  • Patent number: 10535625
    Abstract: According to a first aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a first transistor, a second transistor, at least one source terminal, at least one gate terminal, at least one drain terminal, a source wire, a gate wire, a drain wire and a support part. The support part includes two first support-part edges and two second support-part edges. Each of the two first support-part edges is parallel to a first direction, and the two first support-part edges are spaced apart from each other in a second direction that is perpendicular to the first direction. Each of the two second support-part edges is physically connected to the two first support-part edges. The source wire, the gate wire and the drain wire cross at least one of the two second support-part edges in plan view.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: January 14, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Atsushi Yamaguchi, Junichi Kashiwagi, Hirokatsu Umegami
  • Patent number: 10522462
    Abstract: Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.
    Type: Grant
    Filed: July 28, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 10522477
    Abstract: A method of making a semiconductor package structure includes bonding a plurality of dies to a substrate, wherein a first die of the plurality of dies is larger than a second die of the plurality of dies. The method further includes adhering a first stress relief structure to the substrate at a corner of the substrate, wherein a distance between the first stress relief structure to a closest die of the plurality of dies to the first stress relief structure is a first distance. The method further includes adhering a second stress relief structure to the substrate along a single edge of the substrate, wherein a distance between the second stress relief structure to a closest die of the plurality of dies to the second stress relief structure is the first distance.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsien-Wei Chen
  • Patent number: 10522613
    Abstract: A resistance device includes a substrate, a fin on the substrate, a trench isolation structure formed around the fin. The resistance device further includes at least one first dummy gate structure on the fins, an inter-layer dielectric layer on the trench isolation structure, where the inter-layer dielectric layer covers the fin and the at least one first dummy gate structure. The resistance device further includes a resistance material layer on the inter-layer dielectric layer.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: December 31, 2019
    Assignees: Semiconductor Manufacturing International (Beijing) Corp., Semiconductor Manufacturing International (Shanghai) Corp.
    Inventor: Fei Zhou
  • Patent number: 10522433
    Abstract: A package which comprises a chip carrier made of a first material, a body made of a second material differing from the first material and being arranged on the chip carrier so as to form a cavity, a semiconductor chip arranged at least partially in the cavity, and a laminate encapsulating at least one of at least part of the chip carrier, at least part of the body and at least part of the semiconductor chip.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: December 31, 2019
    Assignee: Infineon Technologies AG
    Inventors: Juergen Hoegerl, Horst Theuss, Gottfried Beer
  • Patent number: 10510731
    Abstract: Package-On-Package (PoP) structures that includes stud bulbs is provided. According to an embodiment, a POP structure includes a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Chung-Shi Liu, Ming-Da Cheng
  • Patent number: 10510674
    Abstract: A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING, COMPANY, LTD.
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen