Patents Examined by Alexander O. Williams
  • Patent number: 11018133
    Abstract: A 3D integrated circuit, the circuit including: a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; where the second wafer is bonded face-to-face on top of the first wafer, where the bonded includes copper to copper bonding; and where the second crystalline substrate has been thinned to a thickness of less than 5 micro-meters.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 25, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
  • Patent number: 11018093
    Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: May 25, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Bharat Bhushan, Juan Boon Tan, Boo Yang Jung, Wanbing Yi, Danny Pak-Chum Shum
  • Patent number: 11011545
    Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Pen Guo, Lee-Chung Lu, Li-Chun Tien
  • Patent number: 11011482
    Abstract: A semiconductor package includes a semiconductor chip, an encapsulant, and an interconnection member. The semiconductor chip has connection pads. The encapsulant encapsulates a portion of the semiconductor chip. The interconnection member includes a first insulating layer disposed on the encapsulant and a portion of the semiconductor chip, a redistribution layer disposed on the first insulating layer, and a second insulating layer disposed on the first insulating layer and the redistribution layer. The redistribution layer is electrically connected to the connection pads of the semiconductor chip, and a thickness of the second insulating layer is greater than a thickness of the first insulating layer.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: May 18, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doo Hwan Lee, Jong Rip Kim, Hyoung Joon Kim, Jin Yul Kim, Kyung Seob Oh
  • Patent number: 11011643
    Abstract: A semiconductor device includes a semiconductor wafer having one or more suspended nanosheet extending between first and second source/drain regions. A gate structure wraps around the nanosheet stack to define a channel region located between the source/drain regions. The semiconductor device further includes a first all-around source/drain contact formed in the first source/drain region and a second all-around source/drain contact formed in the second source/drain region. The first and second all-around source/drain contacts each include a source/drain epitaxy structure and an electrically conductive external portion that encapsulates the source/drain epitaxy structure.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: May 18, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Xu, Chun Wing Yeung, Chen Zhang
  • Patent number: 11004773
    Abstract: First semiconductor devices, a first dielectric material layer, a porous dielectric material layer, and a metal interconnect structure formed within a second dielectric material layer are formed on a front-side surface of a first semiconductor substrate. A via cavity extending through the first semiconductor substrate and the first dielectric material layer are formed. The via cavity stops on the porous dielectric material layer. A continuous network of pores that are free of any solid material therein continuously extends from a bottom of the via cavity to a surface of the metal interconnect structure. A through-substrate via structure is formed in the via cavity. The through-substrate via structure includes a porous metallic material portion filling the continuous network of pores and contacting surface portions of the metal interconnect structure. Etch damage to the first semiconductor devices and metallic particle generation may be minimized by using the porous metallic material portion.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: May 11, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Chen Wu, Peter Rabkin, Masaaki Higashitani
  • Patent number: 11004837
    Abstract: A semiconductor device includes a substrate, a semiconductor device module, and a heat conductor. The semiconductor device module is on the substrate. The semiconductor device module includes an interposer substrate, one or more semiconductor device chips, a covering resin, and a metal film. The one or more semiconductor device chips are on a first surface of the interposer substrate. The covering resin is in contact with the first surface of the interposer substrate and the one or more semiconductor device chips and encloses the one or more semiconductor device chips. The metal film is in contact with the covering resin and covers the covering resin. The heat conductor is in thermal contact with the substrate and the metal film, and has a higher thermal conductivity than the covering resin.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: May 11, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Akiko Fujimaki
  • Patent number: 10998266
    Abstract: A semiconductor device includes a semiconductor chip body having a surface on which a chip pad is disposed, a passivation layer covering the surface of the semiconductor chip body and providing a tapered hole revealing the chip pad, and a redistributed layer (RDL) structure disposed on the passivation layer. The RDL structure includes a first RDL interconnection portion spaced apart from the tapered hole and passing by the tapered hole and a second RDL overlapping pad portion configured to have a bottom portion contacting the revealed chip pad and configured to have a first side surface facing a side surface of the first RDL interconnection portion. A central portion of the first side surface of the second RDL overlapping pad portion extends toward the side surface of the first RDL interconnection portion such that the first side surface is curved.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Bang, Sang Jae Kim, Shin Young Park
  • Patent number: 10998340
    Abstract: A semiconductor device includes a plurality of standard cells. The plurality of standard cells include a first group of standard cells arranged in a first row extending in a row direction and a second group of standard cells arranged in a second row extending in the row direction. The first group of standard cells and the second group of standard cells are arranged in a column direction. A cell height of the first group of standard cells in the column direction is different from a cell height of the second group of standard cells in the column direction.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Pen Guo, Lee-Chung Lu, Li-Chun Tien
  • Patent number: 10998427
    Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Chang, Chiung Wen Hsu, Yu-Ting Weng
  • Patent number: 10991710
    Abstract: A non-volatile memory device includes a vertical state transistor disposed in a semiconductor substrate, where the vertical state transistor is configured to trap charges in a dielectric interface between a semiconductor well and a control gate. A vertical selection transistor is disposed in the semiconductor substrate. The vertical selection transistor is disposed under the state transistor, and configured to select the state transistor.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: April 27, 2021
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Quentin Hubert, Abderrezak Marzaki, Julien Delalleau
  • Patent number: 10991792
    Abstract: An organic light emitting diode display includes a plurality of pixels. At least one pixel is connected to a scan line receive a scan signal, a data line to receive a data signal, and voltage line to receive a driving voltage. The at least one pixel includes a switching transistor including a switching drain electrode to output the data voltage, a driving transistor including a driving source electrode connected to the switching drain electrode, and an organic light emitting diode connected to a driving drain electrode of the driving transistor. The driving source electrode is separated from the data line.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: April 27, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Mi Hae Kim, Min Ho Ko, Seung Woo Sung, Ki Myeong Eom, Jin Jeon
  • Patent number: 10991806
    Abstract: A structure of memory device is provided. The structure of memory device includes a first gate structure, disposed on a substrate, wherein the first gate structure is for storing charges. In addition, a second gate structure is disposed on the substrate. An insulating layer is in contact between the first gate structure and the second gate structure. An isolation structure integrated with the insulating layer is between the first gate structure and the second gate structure and at a top portion of the first gate structure and the second gate structure. The isolation structure provides an isolation distance between the first gate structure and the second gate structure.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: April 27, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chin-Chin Tsai
  • Patent number: 10978431
    Abstract: A semiconductor package includes a lower substrate, a connection substrate coupled to the lower substrate, the connection substrate having a lateral portion surrounding a cavity, and a first conductive pattern on a top surface of the lateral portion, a lower semiconductor chip on the lower substrate, the lower semiconductor chip being in the cavity of the connection substrate, and the lower semiconductor chip including a second conductive pattern on a top surface of the lower semiconductor chip, a bonding member connecting the first conductive pattern and the second conductive pattern to each other, and a top package on the first conductive pattern and the second conductive pattern.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongbo Shim, Ji Hwang Kim, Chajea Jo, Sang-Uk Han
  • Patent number: 10978370
    Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Jan Pei, Wei-Yu Chen, Chia-Shen Cheng, Chih-Chiang Tsao, Cheng-Ting Chen, Chia-Lun Chang, Chih-Wei Lin, Hsiu-Jen Lin, Ching-Hua Hsieh, Chung-Shi Liu
  • Patent number: 10978418
    Abstract: A method of forming an electrical contact and a method of forming a chip package are provided. The methods may include arranging a metal contact structure including a non-noble metal and electrically contacting the chip, arranging a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 13, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Joachim Mahler, Michael Bauer, Jochen Dangelmaier, Reimund Engl, Johann Gatterbauer, Frank Hille, Michael Huettinger, Werner Kanert, Heinrich Koerner, Brigitte Ruehle, Francisco Javier Santos Rodriguez, Antonio Vellei
  • Patent number: 10978469
    Abstract: A semiconductor storage device includes a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a barrier metal layer provided on the insulating layer; an aluminum compound layer provided on the barrier metal layer; an amorphous layer provided on the aluminum compound layer and including a material that vaporizes upon its chemical reaction with fluorine; and a metal layer provided on the amorphous layer.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: April 13, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kensei Takahashi, Takashi Asano, Satoshi Wakatsuki
  • Patent number: 10971650
    Abstract: A light emitting device includes a stacked structure and a first insulating layer covering at least side surfaces of the stacked structure including a p-type and n-type semiconductor layers, a light emitting layer sandwiched between the p-type and n-type semiconductor layers, an n-type electrode on the n-type semiconductor layer, an n-type contact layer sandwiched between the n-type semiconductor layer and the n-type electrode, a p-type electrode on the p-type semiconductor layer, an n-type contact pad on the n-type electrode, a p-type contact pad on the p-type electrode, and a semiconductor reflector between the light emitting layer and the n-type contact layer including multiple periods, each period including at least a first layer and at least a second layer having a refractive index different from a refractive index of the first layer. The light emitting device could be applied to wide color gamut (WCG) backlight modules or ultra-thin backlight modules.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: April 6, 2021
    Assignee: Lextar Electronics Corporation
    Inventor: Shiou-Yi Kuo
  • Patent number: 10968348
    Abstract: Novel thermoplastic polyhydroxyether-based compositions for use as a laser-releasable composition for temporary bonding and laser debonding processes are provided. The inventive compositions can be debonded using various UV lasers, leaving behind little to no debris. The layers formed from these compositions possess good thermal stabilities and are soluble in commonly-used organic solvents (e.g., cyclopentanone). The compositions can also be used as build-up layers for RDL formation.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 6, 2021
    Assignee: Brewer Science, Inc.
    Inventors: Xiao Liu, Qi Wu, Rama Puligadda, Dongshun Bai, Baron Huang
  • Patent number: 10964759
    Abstract: A display device includes a display element configured to generate a first color light, an encapsulation member on the display element and including an inorganic layer at an outermost portion thereof, a color conversion layer on the encapsulation member and including a first color conversion part configured to transmit the first color light, a second color conversion part configured to convert the first color light into a second color light, and a third color conversion part configured to convert the first color light into a third color light, and a buffer layer between the encapsulation member and the color conversion layer, wherein a difference in refractive index between the buffer layer and the inorganic layer is about 0.5 or less.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: March 30, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Soodong Kim, Sunyoung Kwon, Songyi Kim, Jinwon Kim, Kyoungwon Park