Abstract: A chip stack assembly uses a monolithic metallic multilevel connector to both join connections on at different heights on the top sides at the of the chips, and to provide a large, robust connection surface on top of top of the assembly.

Abstract: A microwave device includes: a multilayer resin substrate being a first multilayer resin substrate; an IC being a radio frequency circuit provided on the multilayer resin substrate and electrically connected to the multilayer resin substrate; a heat spreader provided on a side opposite to the multilayer resin substrate across the IC, and in contact with the IC; a mold resin covering the periphery of the IC and the heat spreader; and a conductive film covering the mold resin and the heat spreader, where an inner side of the conductive film is in contact with the heat spreader, and the conductive film is electrically connected to a ground via hole of the multilayer resin substrate.

Abstract: A chip package and method for fabricating the same are provided which utilize a cover having one or more windows formed through one or more sidewalls to provide excellent resistance to warpage while allowing access to an internal volume of the chip package. In one example, the chip package includes a package substrate, an integrated circuit (IC) die, and a cover disposed over the IC die. The cover includes a lower surface facing the IC die, an upper surface facing away from the IC die, a lip extending from the lower surface, and a first sidewall extending from a first edge of the upper surface to the bottom of the lip. The lip is secured to the package substrate and encloses a volume between the lower surface and the package substrate. The IC die resides in the volume. A first elongated window is formed through the first sidewall and exposes the volume through the cover.

Abstract: A semiconductor structure includes a porous semiconductor segment adjacent to a first region of a substrate, and a crystalline epitaxial layer situated over the porous semiconductor segment and over the first region of the substrate. A first semiconductor device is situated in the crystalline epitaxial layer over the porous semiconductor segment. The first region of the substrate has a first dielectric constant, and the porous semiconductor segment has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor segment reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer over the first region of the substrate, and an electrical isolation region separating the first and second semiconductor devices.

Abstract: An organic thin film that imparts an excellent electron injection property when it is used as an electron injection layer of an organic EL device and a method for producing the organic thin film are provided. An organic thin film at least includes: a first material which is an organic material having an acid dissociation constant pKa of 1 or greater; and a second material which transports an electron. The first material is at least one selected from the group consisting of tertiary amines, phosphazene compounds, guanidine compounds, heterocyclic compounds containing an amidine structure, hydrocarbon compounds having a ring structure, and ketone compounds.

Abstract: A method includes forming a metallic interconnect structure on a semiconductor substrate where the metallic interconnect structure comprises a plurality of metal lines with adjacent metal lines separated by a gap therebetween. The method further includes selectively depositing a first low-k dielectric material onto the semiconductor substrate and onto exposed surfaces of the metal lines of the metallic interconnect structure to form a barrier on at least the metal lines. The barrier is configured to minimize oxidation and diffusion of metal of the metal lines. The method also includes depositing a flowable second low-k dielectric material onto the semiconductor substrate to form a dielectric layer encapsulating the barrier and the metallic interconnect structure.

Abstract: A semiconductor structure includes a substrate having a first dielectric constant, a porous semiconductor layer situated over the substrate, and a crystalline epitaxial layer situated over the porous semiconductor layer. A first semiconductor device is situated in the crystalline epitaxial layer. The porous semiconductor layer has a second dielectric constant that is substantially less than the first dielectric constant such that the porous semiconductor layer reduces signal leakage from the first semiconductor device. The semiconductor structure can include a second semiconductor device situated in the crystalline epitaxial layer, and an electrical isolation region separating the first and second semiconductor devices.

Abstract: Techniques to enable bottom barrier free interconnects without voids. In one aspect, a method of forming interconnects includes: forming metal lines embedded in a dielectric; depositing a sacrificial dielectric over the metal lines; patterning vias and trenches in the sacrificial dielectric down to the metal lines, with the trenches positioned over the vias; lining the vias and trenches with a barrier layer; depositing a conductor into the vias and trenches over the barrier layer to form the interconnects; forming a selective capping layer on the interconnects; removing the sacrificial dielectric in its entirety; and depositing an interlayer dielectric (ILD) to replace the sacrificial dielectric. An interconnect structure is also provided.

Abstract: A package structure includes a base material, at least one electronic device, at least one dummy pillar and an encapsulant. The electronic device is electrically connected to the base material. The dummy pillar is disposed on the base material. The encapsulant covers the electronic device and a top end of the dummy pillar.

Abstract: A microwave device includes: a multilayer resin substrate being a first multilayer resin substrate; an IC being a radio frequency circuit provided on the multilayer resin substrate and electrically connected to the multilayer resin substrate; a heat spreader provided on a side opposite to the multilayer resin substrate across the IC, and in contact with the IC; a mold resin covering the periphery of the IC and the heat spreader; and a conductive film covering the mold resin and the heat spreader, where an inner side of the conductive film is in contact with the heat spreader, and the conductive film is electrically connected to a ground via hole of the multilayer resin substrate.

Abstract: Provided is a memory device including an array of memory cells. A first bit-line coupled to memory cells of a first column of the array of memory cells. The first bit-line is disposed on a first metal layer. A second bit-line is coupled to the first bit-line. The second bit-line is disposed on a second metal layer and coupled to the first bit-line by at least one via. A word line is coupled to a row of the array of memory cells.

Abstract: A semiconductor structure includes a semiconductor substrate, a porous semiconductor region within the semiconductor substrate, and through-substrate via (TSV) within the porous semiconductor region. The porous semiconductor region causes the semiconductor structure and/or the TSV to withstand thermal and mechanical stresses. Alternatively, the semiconductor structure includes a semiconductor buffer ring within the porous semiconductor region, and the TSV within the semiconductor buffer ring.

Abstract: An interconnect structure for a semiconductor device includes a plurality of unit cells. Each unit cell is formed of interconnected conducting segments. The plurality of unit cells forms a conducting lattice.

Abstract: A semiconductor device includes: an insulation circuit substrate including a metal layer and an insulation substrate, the metal layer being formed on one surface of the insulation substrate, a connecting member having a cylindrical shape joined to the metal layer via a bonding material, a terminal pin inserted in the connecting member, and a reinforcement member having a cylindrical shape disposed on an outer periphery of the connecting member. The reinforcement member is made of a material having a hardness greater than that of the connecting member.

Abstract: A thin, sheetlike, electronic, self-powered component including at least a display device and/or a sensor, as well as an energy source or a combination of the preceding is provided. Furthermore, the integration of this electrical component in existing products, especially printing and paper products, without the objects having to be damaged or destroyed is provided.

Abstract: A semiconductor device is provided that has high electromagnetic wave shielding properties while exhibiting good heat dissipation. The semiconductor device includes a semiconductor package bonded onto a circuit board, an electromagnetic wave absorbing layer covering surfaces of the semiconductor package other than a surface bonded to the circuit board, and an electromagnetic wave reflecting layer covering the electromagnetic wave absorbing layer on a side remote from the semiconductor package, in which the electromagnetic wave absorbing layer is made of resin containing magnetic particles or carbon, and the electromagnetic wave reflecting layer is made of resin containing conductive particles.

Abstract: Methods of manufacturing a biocompatible, hermetic feedthrough monolithically integrated with a biocompatible ribbon cable are described, as well as the resulting devices themselves. The hermetic feedthrough is created by placing glass over a mold of doped silicon or other material with a higher melting temperature than the glass and heating it to reflow the glass into the mold. The glass is then ground or otherwise removed to reveal a flat surface, and tiny pillars that were in the mold are isolated in the glass to form electrically conductive vias. The flat surface is used to cast a polymer and build up a ribbon cable, photolithographically or otherwise, that is monolithically attached to the vias.

Abstract: A 3D device including: a first level including first single crystal transistors overlaid by a second level including second single crystal transistors; a third level including third single crystal transistors, the second level is overlaid by the third level; a fourth level including fourth single crystal transistors, the third level is overlaid by the fourth level; first bond regions including first oxide to oxide bonds, where the first bond regions are between the first level and the second level; second bond regions including second oxide to oxide bonds, where the second bond regions are between the second level and the third level; and third bond regions including third oxide to oxide bonds, where the third bond regions are between the third level and the fourth level, where the second level, third level, and fourth level each include one array of memory cells, and where the one array of memory cells is a DRAM type memory.

Abstract: A Fan-Out package having a main die and a dummy die side-by-side is provided. A molding material is formed along sidewalls of the main die and the dummy die, and a redistribution layer having a plurality of vias and conductive lines is positioned over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die.

Abstract: The invention relates to a modular element (2) comprising a stratification of first and second electroconductive plates (PH2, PB2) which are separated by an intermediate dielectric layer (CD2) and at least one electronic power switching chip (CP1, CP2) which is implanted between the first and second plates, the chip having a upper face comprising a first power electrode and a switching control electrode and a lower face comprising a second power electrode, and the first and second power electrodes being in electrical continuity respectively with the first and second plates.