Abstract: A display panel is provided and includes a first data line and a first signal line which are disposed at a display area, a second data line and a second signal line which are disposed at a non-display area. A portion of the second data lines, a portion of the second signal lines, and the first data line or the first signal line are all on a same film layer structure of the display panel.

Abstract: An image sensor may include a pixel array including a plurality of pixel blocks structured to convert light into electrical signals. Each of the plurality of pixel blocks may include a first light receiving circuit including a plurality of unit pixels which share a first floating diffusion; a second light receiving circuit arranged adjacent to the first light receiving circuit in a second direction, and including a plurality of unit pixels which share a second floating diffusion; a first driving circuit and a second driving circuit positioned between the first light receiving circuit and the second light receiving circuit, and aligned in a first direction crossing the second direction; and an intercoupling circuit configured to electrically couple the first floating diffusion, the second floating diffusion, the first driving circuit and the second driving circuit.

Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

Abstract: An electronic component housing package includes an insulating substrate having a first principal face and a second principal face opposing the first principal face; external connection conductors provided on the second principal face; and connection conductors provided so as to extend from outer peripheral ends of the external connection conductors to outer peripheral ends of the insulating substrate, respectively. The connection conductors are provided so as to be curved convexly toward a first principal face side over a range from the outer peripheral ends of the external connection conductors to the outer peripheral ends of the insulating substrate in a vertical cross-sectional view of the electronic component housing package and so that a distance from each of the connection conductors to the second principal face is gradually increased in a thickness direction of the insulating substrate. Insulating bodies are provided so as to cover the connection conductors, respectively.

Abstract: A semiconductor light-emitting device capable of suppressing the influence of thermal expansion on a light-emitting element during operation of the device and improving light-emitting characteristics is provided. The semiconductor light-emitting device includes: a substrate having a through hole, a metal core fitted into the through hole via a resin layer and penetrating through the substrate; a thermally-conductive film formed in the region of the upper surface of the metal core and having a flat surface; and a semiconductor light-emitting element bonded to the flat surface of the thermally-conductive film with an adhesive layer interposed therebetween. The outer edge of the thermally-conductive film is separated from the outer edge of the upper surface of the metal core.

Abstract: A method for manufacturing a display panel to comprise light emitting elements which together present a flat and wrinkle-free top surface includes a substrate, a TFT array layer arranged on the substrate, an insulating layer arranged on a surface of the TFT array layer away from the substrate, and light emitting elements arranged on a surface of the insulating layer away from the TFT array layer. Top surfaces of the light emitting elements away from the insulating layer are coplanar. Thicknesses of the light emitting elements are different from each other, and thicknesses of the insulating layer below different light emitting elements are different from each other. A display panel applying the method is also disclosed.

Abstract: A semiconductor package includes a package substrate, a first chip stack, a second chip stack, and a supporting block. The first chip stack includes first semiconductor chips stacked on the package substrate to be offset in a first direction, and the second chip stack includes second semiconductor chips stacked on the first chip stack to be offset in a second direction. The supporting block includes a through via structure. The second chip stack is supported by the first chip stack and the supporting block.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.

Abstract: An electronic package unit, a manufacturing method thereof and an electronic device are disclosed. The manufacturing method includes: providing an insulation substrate, wherein the insulation substrate has a first surface and a second surface opposite to the first surface; forming a plurality of sub-matrix circuits on the insulation substrate, wherein each sub-matrix circuit comprises at least one thin film transistor; disposing at least one functional chip on the first surface, wherein the functional chip is electrically connected with the sub-matrix circuit; forming a plurality of through-holes on the insulation substrate and disposing a conductive material in the through-holes, so that the functional chip is electrically connected to the second surface through the sub-matrix circuits and the conductive material; forming a protection layer on the first surface to cover the functional chips; and cutting the insulation substrate and the protection layer to form a plurality of electronic package units.

Abstract: A display device and a method of manufacturing the same are disclosed. The display device includes a substrate (100), and a patterned polysilicon layer, a patterned gate insulating layer and a patterned first conductive layer stacked on the substrate in sequence. The patterned polysilicon layer includes a number of polysilicon blocks (110) doped with impurities. The patterned first conductive layer includes a number of data lines (120) each partially overlapping a corresponding polysilicon block to form a compensating capacitor.

Abstract: A crack detection chip includes a chip which includes an internal region and an external region surrounding the internal region, a guard ring formed inside the chip along an edge of the chip to define the internal region and the external region, an edge wiring disposed along an edge of the internal region in the form of a closed curve and a pad which is exposed on a surface of the chip and is connected to the edge wiring. The edge wiring is connected to a Time Domain Reflectometry (TDR) module which applies an incident wave to the edge wiring through the pad, and detects a reflected wave formed in the edge wiring to detect a position of a crack.

Abstract: An integrated electronic device includes a semiconductor body and a passivation structure including a frontal dielectric layer bounded by a frontal surface. A conductive region forms a via region, extending into a hole through the frontal dielectric layer. An overlaid redistribution region extends over the frontal surface. A barrier structure includes at least a first barrier region extending into the hole and surrounding the via region. The first barrier region extends over the frontal surface. A first coating layer covers the top and the sides of the redistribution region and a second coating layer covers the first coating layer. A cavity extends between the redistribution region and the frontal surface and is bounded on one side by the first coating layer and on the other by the barrier structure.

Abstract: A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

Abstract: The disclosure provides a fabricating method of a QLED device and a QLED device. In the fabricating method of a QLED device, a mixed light-emitting layer is formed by doping a quantum dot material with a second hole transporting material having a valence band energy level between the quantum dot material and the first hole transporting material; a stepped barrier between the first hole transporting material and the doped second hole transporting material is used to enhance the hole injection; simultaneously, the first hole transporting material with a higher valence band energy level can block the electrons on one side of the hole transport layer close to the cathode to weaken the injection of electrons into the mixed light-emitting layer, thereby promoting the balance of carriers in the mixed light-emitting layer, improving the carrier recombination efficiency, and then improving the luminous efficiency and brightness of the QLED device.

Abstract: A semiconductor die, which includes a first semiconductor device, a first passivation layer, and a first interconnect bump, is disclosed. The first passivation layer is over the first semiconductor device, which includes a first group of device fingers. The first interconnect bump is thermally and electrically connected to each of the first group of device fingers. Additionally, the first interconnect bump protrudes through a first opening in the first passivation layer.

Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.

Abstract: A method for manufacturing an IGZO thin-film transistor includes: manufacturing a buffer layer, an active layer, a gate electrode layer, and a gate insulator layer in sequence on a substrate, and performing a patterning process; depositing a transparent insulating metal oxide layer on the patterned buffer layer, the active layer, the gate electrode layer, and the gate insulator layer by sputtering, and annealing the transparent insulating metal oxide layer so as to improve electric properties of a thin-film transistor; depositing a dielectric layer on the transparent insulating metal oxide layer, and patterning the dielectric layer and the transparent insulating metal oxide layer by means of a photolithography process and a dry etch process; depositing S/D (source/drain) contact regions on the dielectric layer; and performing a patterning process.

Abstract: An organic light emitting diode device and a manufacture method thereof, a display panel are provided. The organic light emitting diode device includes a plurality of pixels, each of the pixels includes at least two sub-pixels that are capable of generating light of different colors, and each of the sub-pixels includes a first electrode, a second electrode, and a light emitting layer between the first electrode and the second electrode; and each of the sub-pixels further includes a microcavity adjusting layer including pores, the microcavity adjusting layer is on a side of the first electrode that is far away from the light emitting layer, and a porosity and an average aperture of the pores in the microcavity adjusting layer of each of the sub-pixels that are capable of generating light of different colors are different.

Abstract: A package structure and method for forming the same are provided. The package structure includes a package component, a device die disposed over the package component, and the device die has a first height. The package structure also includes a dummy die adjacent to the device die, wherein the dummy die has a second height smaller than the first height. The package structure further includes a package layer between the device die and the dummy die.

Abstract: Semiconductor devices with controllers under stacks of semiconductor packages and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a package substrate, a controller attached to the package substrate, and at least two semiconductor packages disposed over the controller. Each semiconductor package includes a plurality of semiconductor dies. The semiconductor device further includes an encapsulant material encapsulating the controller and the at least two semiconductor packages.