Patents Examined by Alexander Oscar Williams
  • Patent number: 10373895
    Abstract: A semiconductor device includes a first lead frame, a second lead frame, a first semiconductor chip, and an encapsulation material. The first lead frame includes a first die pad having a first surface and a second surface opposite to the first surface. The second lead frame includes a second die pad having a first surface and a second surface opposite to the first surface. The first surface of the second die pad faces the first surface of the first die pad. The first semiconductor chip is attached to the first surface of the first die pad. The encapsulation material encapsulates the first semiconductor chip and portions of the first lead frame and the second lead frame. The encapsulation material has a first surface aligned with the second surface of the first die pad and a second surface aligned with the second surface of the second die pad.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: August 6, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Edward Fuergut, Martin Gruber, Wolfgang Scholz, Ralf Otremba
  • Patent number: 10361135
    Abstract: A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: July 23, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Baek Ki, Tark-Hyun Ko, Kun-Dae Yeom, Yong-Kwan Lee, Keun-Ho Jang
  • Patent number: 10319650
    Abstract: A semiconductor package including a redistribution substrate, and a semiconductor chip mounted on the redistribution substrate, the semiconductor chip having a conductive pad on one surface thereof may be provided. The redistribution substrate may include a first passivation pattern on the conductive pad, the first passivation pattern exposing a portion of the conductive pad, and a redistribution pattern covering the portion of the conductive pad exposed by the first passivation pattern and surrounding the first passivation pattern.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongyoun Kim, Seokhyun Lee
  • Patent number: 10261498
    Abstract: Provided is a numerical controller including a wait management table that stores wait management information of each machining program, a wait controller that performs wait control of each axis based on the wait management information with respect to an axis controller that controls each axis of each path, and a management unit that updates the wait management information of each machining program stored in the wait management table.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: April 16, 2019
    Assignee: FANUC Corporation
    Inventor: Yuu Oota
  • Patent number: 10249561
    Abstract: A printed wiring board includes a support plate, and a build-up wiring layer including resin insulating layers and conductor layers and having a first surface and a second surface on the opposite side with respect to the first surface such that the support plate is positioned on the first surface of the build-up wiring layer. The resin insulating layers in the build-up wiring layer include a first resin insulating layer that forms the second surface of the build-up wiring layer, and the build-up wiring layer includes first conductor pads embedded in the first resin insulating layer such that each of the first conductor pads has an exposed surface exposed from the second surface of the build-up wiring layer.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 2, 2019
    Assignee: IBIDEN CO., LTD.
    Inventors: Teruyuki Ishihara, Haiying Mei, Hiroyuki Ban
  • Patent number: 10249560
    Abstract: The object is to suppress rupture of the soldering balls when an atmosphere varying from a high temperature to a low temperature is repeated. A semiconductor device includes a semiconductor integrated circuit and a substrate. The semiconductor integrated circuit is, for example, a semiconductor chip. The coefficient of thermal expansion is different between the semiconductor integrated circuit and the substrate. The substrate includes a plurality of soldering balls on the opposite surface to the surface where the semiconductor integrated circuit is mounted. The substrate does not have the soldering balls at a position corresponding to at least one side of the fringe of the semiconductor integrated circuit.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: April 2, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Takafumi Betsui
  • Patent number: 10236338
    Abstract: A SiC single crystal seed of the present invention has a main surface with an offset angle of at least 2° but not more than 20° relative to the {0001} plane, and at least one sub-growth surface, wherein the sub-growth surface includes an initial facet formation surface that is on the offset upstream side of the main surface and has an inclination angle ? relative to the {0001} plane with an absolute value of less than 2° in any direction, and the initial facet formation surface has a screw dislocation starting point.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: March 19, 2019
    Assignee: SHOWA DENKO K.K.
    Inventors: Yuuki Furuya, Tomohiro Shonai, Yasushi Urakami, Itaru Gunjishima
  • Patent number: 10236189
    Abstract: A heat sink can be attached to a heat-producing electronic device by aligning an adhesive material to a surface of the heat sink, applying the adhesive material to the surface to form an outer perimeter and applying, within the outer perimeter, a thermally conductive material to the surface. The surface of the heat sink and a surface of the heat-producing electronic device can then be aligned, and the heat sink can be assembled to the heat-producing electronic device by bringing the heat-producing electronic device surface into contact with the adhesive material. The heat sink can then be affixed to the heat-producing electronic device by applying a compressive force to the assembly to activate the adhesive material.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karl Stathakis, Phillip V. Mann, Mark K. Hoffmeyer
  • Patent number: 10229942
    Abstract: The present technology relates to a solid state imaging device that enables a reduction in the manufacturing cost of the solid state imaging device, and an electronic apparatus. A first substrate including a pixel circuit having a pixel array unit and a second substrate including a first and a second signal processing circuit arranged side by side across a scribe area are stacked. The second substrate includes a first moisture-resistant ring surrounding at least part of a periphery of the first signal processing circuit, a second moisture-resistant ring surrounding at least part of a periphery of the second signal processing circuit, a third moisture-resistant ring surrounding at least part of a periphery of the second substrate in a layer different from the first and second moisture-resistant rings, and a barrier unit separating a first area between the first and second moisture-resistant rings and a second area.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: March 12, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hidetoshi Oishi, Kunihiko Izuhara
  • Patent number: 10204881
    Abstract: A power overlay (POL) structure includes a power device having at least one upper contact pad disposed on an upper surface of the power device, and a POL interconnect layer having a dielectric layer coupled to the upper surface of the power device and a metallization layer having metal interconnects extending through vias formed through the dielectric layer and electrically coupled to the at least one upper contact pad of the power device. The POL structure also includes at least one copper wirebond directly coupled to the metallization layer.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: February 12, 2019
    Assignee: General Electric Company
    Inventors: Arun Virupaksha Gowda, Paul Alan McConnelee
  • Patent number: 10199336
    Abstract: An antenna semiconductor package device includes a first conductive layer, a second conductive layer, a first conductive element and a first directing element. The second conductive layer is over the first conductive layer and separated from the first conductive layer. The first conductive element connects the first conductive layer to the second conductive layer. The first directing element is adjacent to the first conductive layer and separated from the first conductive layer by a first gap. The first conductive element, the first conductive layer and the second conductive layer define a waveguide cavity and a radiation opening.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: February 5, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-En Hsu, Huei-Shyong Cho, Shih-Wen Lu
  • Patent number: 10177070
    Abstract: A flexible graphite sheet support structure forms a thermal management arrangement for device having a heat source. The flexible graphite sheet support structure includes first and second spaced apart support members and a flexible graphite sheet secured to the spaced apart support members forming a free standing flex accommodating section that spans between them. Curve retention members having convex curved surfaces are used to keep the flex accommodating section in a bell shaped curve while preventing the flexible graphite sheet from exceeding a minimum bend radius. The thermal management arrangement formed by the flexible graphite sheet support structure enables the flexible graphite sheet to move heat from one support structure to the other while reducing the transmission of vibration between them and allowing relative movement between the spaced apart support structures.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: January 8, 2019
    Assignee: NeoGraf Solutions, LLC
    Inventors: Frank P. Dornauer, Greg P. Kramer, Martin D. Smalc
  • Patent number: 10173890
    Abstract: A box for a microelectronic device includes a first portion and a second portion able to be assembled in order to define, in an assembled position, a housing space for the microelectronic device. A face of the first portion is facing a face of the second portion in the assembled position. The first zones facing the faces form an interface for attaching the first portion and second portion. The second zones face faces forming a cavity for receiving the microelectronic device. At least one among the first portion and the second portion includes at least one element for electrical connection. The first portion and the second portion can apply at least one connection pad of the microelectronic device on the element for connection in the assembled position.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: January 8, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Jean-Charles Souriau
  • Patent number: 10177129
    Abstract: A display device includes a display panel including a substrate, pixels provided on the substrate, and first lines connected to the pixels, the display device having a bending area where the display panel is bent. The display panel also includes a chip on film overlapping with a portion of the display panel and having second lines, an anisotropic conductive film provided between the chip on film and the display panel connecting the first lines and the second lines, and a coating layer covering the bending area and one end of the chip on film. In such a device, lines of the chip on film may be prevented from being corroded as they may be spaced apart from an edge of an insulating film.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: January 8, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jun Namkung, Soon Ryong Park, Ju Yeop Seong, Hyun Kyu Choi
  • Patent number: 10170541
    Abstract: A semiconductor device includes a plurality of electrode structures formed on a substrate; and an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures The upper supporter group includes a plurality of supporters, and at least some of the plurality of supporters each have an upper surface and a lower surface. One of the upper surface and the lower surface has a curved profile, and the other surface has a flat profile.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: January 1, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-young Yi, Youn-seok Choi, Young-min Ko, Mun-jun Kim, Hong-gun Kim, Seung-heon Lee
  • Patent number: 10163746
    Abstract: A semiconductor package and manufacturing method thereof includes a chip member installed on an upper surface, a lower surface, or both of a substrate. The semiconductor package and manufacturing method thereof also include a mold part stacked embedding the chip member, a connection member disposed at a center portion of the mold part, and a solder part formed on a portion of the connection member.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: December 25, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jong In Ryu, Ki Joo Sim, Do Jae Yoo, Ki Ju Lee, Jin Su Kim
  • Patent number: 10163743
    Abstract: An air cavity package includes a flange and a pedestal extending upward from the flange. A dielectric frame is joined to the flange and surrounds the pedestal. The semiconductor die is placed on the pedestal, which reduces the length of the wires joining the die to the leads of the air cavity package.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: December 25, 2018
    Assignee: MATERION CORPORATION
    Inventors: Richard J. Koba, Chee Kong Lee, Wei Chuan Goh, Sin Yee Chin
  • Patent number: 10163834
    Abstract: A chip package structure includes a chip, an encapsulant, a dielectric layer and a patterned circuit layer. The chip includes an active surface and a plurality of pads disposed on the active surface. The encapsulant encapsulates the chip and exposes active surface, wherein the encapsulant includes a concave surface and a back surface opposite to the concave surface, the concave surface exposes the active surface and is dented toward the back surface. The dielectric layer covers the concave surface and the active surface and includes a plurality of openings exposing the pads, wherein the opening includes a slanted side surface and the angle between the slanted side surface and the active surface is an acute angle. The patterned circuit layer is disposed on the dielectric layer and electrically connected to the pads through the openings.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: December 25, 2018
    Assignee: Powertech Technology Inc.
    Inventors: Li-Chih Fang, Hung-Hsin Hsu, Nan-Chun Lin, Shang-Yu Chang Chien
  • Patent number: 10163802
    Abstract: A method of forming a package and a package are provided. The method includes placing a main die and a dummy die side by side on a carrier substrate. The method also includes forming a molding material along sidewalls of the main die and the dummy die. The method also includes forming a redistribution layer comprising a plurality of vias and conductive lines over the main die and the dummy die, where the plurality of vias and the conductive lines are electrically connected to connectors of the main die. The method also includes removing the carrier substrate.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semicondcutor Manufacturing Company, Ltd.
    Inventors: Yan-Fu Lin, Chen-Hua Yu, Meng-Tsan Lee, Wei-Cheng Wu, Hsien-Wei Chen
  • Patent number: 10157893
    Abstract: Package-On-Package (PoP) structures including stud bulbs and methods of forming PoP structures are provided. A structure may include a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Mirng-Ji Lii, Chung-Shi Liu, Ming-Da Cheng