Abstract: A package is formed by a thermal base and a leadframe assembly. The thermal base includes a body of thermally conductive material having a top surface, wherein the top surface of the body includes a pedestal. An integrated circuit chip is mounted to the pedestal, the integrated circuit chip including bonding pads. The leadframe assembly includes leads and an encapsulant ring that partially embeds the leads. The leadframe assembly is mounted to the top surface of said body surrounding the pedestal. The pedestal is configured with a thickness that positions the bonding pad at a height substantially coplanar with the leads. Bonding wires extend from the bonding pads to the leads with a shortened length so as to provide for improved electrical characteristics of frequency response, impedance and inductance.

Abstract: In an example, a silicone-based thermal interface material includes a thermally conductive material and a silicone-based polymeric material having a solubility parameter that is not less than 9.09 cal1/2 cm?3/2.

Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.

Abstract: An integrated circuit device includes a first conductive line and a second conductive line that are spaced apart from each other and extend in a first direction to be parallel to each other; and a contact pad including a pad body including a first branch portion from which the first conductive line branches and a second branch portion from which the second conductive line branches and a loop branch portion that is located between the first branch portion and the second branch portion and protrudes from the pad body. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor package structure is disclosed. The semiconductor package structure includes: a substrate having a front surface and a back surface; a chip-on-interposer structure mounted on the front surface of the substrate; a back side stiffener mounted over the back surface of the substrate and surrounding a projection of the chip-on-interposer structure from a back surface perspective; and a plurality of conductive bumps mounted on the back surface of the substrate.

Abstract: A conductive connection structure includes a semiconductor substrate, a conductive pillar, and a stress buffer layer. The conductive pillar is in the semiconductor substrate. The stress buffer layer is between the semiconductor substrate and the conductive pillar. The conductive pillar has a protruding portion penetrating through the stress buffer layer.

Abstract: A film-like epoxy resin composition includes an epoxy resin (A); a curing agent (B); a cure accelerator (C);an inorganic filler (D); and an organic solvent (E). The film-like epoxy resin composition satisfies all the following requirements (1) to (4): (1) at least one of the epoxy resin (A) and the curing agent (B) contains a component being a liquid at 25° C. in an amount of 30% by mass or more based on the total mass of the epoxy resin (A) and the curing agent (B); (2) the content of a volatile portion that volatilizes by being heated at 180° C. for 10 minutes is 0.2% to 1.5% by mass based on the total amount of the epoxy resin composition; (3) the minimum melt viscosity in temperature rising from 40° C. to 200° C. is 800 Pa·s or less; and (4) the film thickness is 50 to 500 ?m.

Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

Abstract: A highly reliable display device or electronic appliance is provided. The display device or a light-emitting device includes a substrate; a light-emitting element including a first electrode, an EL layer, and a second electrode; an organic resin film in contact with the light-emitting element; and an oxide semiconductor film in contact with the light-emitting element and the organic resin film. The oxide semiconductor film is in contact with the first electrode or the second electrode included in the light-emitting element. The oxide semiconductor film is in contact with an exposed portion of the organic resin film, typically, a side surface of the organic resin film. The light-emitting element and the organic resin film are positioned between the substrate and the oxide semiconductor film.

Abstract: A water level package includes a substrate, a plurality of semiconductor chips mounted on the substrate, and molding members that contact the substrate and the plurality of semiconductor chips and are formed on the substrate. The molding members include two or more molding members that have coefficients of thermal expansion (CTEs) different from each other.

Abstract: Various embodiments of a feedthrough assembly and methods of forming such assemblies are disclosed. In one or more embodiments, the feedthrough assembly can include a non-conductive substrate and a feedthrough. The feedthrough can include a via from an outer surface to an inner surface of the non-conductive substrate, a conductive material disposed in the via, and an external contact disposed over the via on the outer surface of the non-conductive substrate. The external contact can be electrically coupled to the conductive material disposed in the via. And the external contact can be hermetically sealed to the outer surface of the non-conductive substrate by a bond surrounding the via. In one or more embodiments, the bond can be a laser bond.

Abstract: A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second etch stop layer over and in direct contact with the first dielectric layer, a second dielectric layer over and in direct contact with the first etch stop layer, a stress reduction layer over and in direct contact with the second dielectric layer, a third etch stop layer over and in direct contact with the stress reduction layer and a metal structure over the metal via, wherein the metal structure comprises a lower portion in the second etch stop layer and the second dielectric layer and an upper portion in the stress reduction layer, wherein a top surface of the metal structure is level with a top surface of the stress reduction layer.

Abstract: A package structure including a substrate, a first lead frame, a first metal layer, at least one chip, a base and a second metal layer is provided. The base includes a plurality of openings. The first lead frame is embedded in the substrate and includes a plurality of first pads, where the openings expose the first pads. The first metal layer covers the exposed first pads. The chip is disposed on the substrate and electrically connected to the first metal layer and the first pads. The base covers the substrate with its bonding surface. The second metal layer covers a base surface of the base.

Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.

Abstract: A method for an interconnect structure including: forming a hard mask layer on a semiconductor substrate having a wiring line; patterning the hard mask layer to form a patterned hard mask layer having a hard mask layer opening; depositing a dielectric stack on the patterned hard mask layer and in the hard mask layer opening; patterning the dielectric stack to form a via opening aligned with the hard mask layer opening and to expose the wiring line through the via opening and the hard mask layer opening, a bottom of the via opening defined by the hard mask layer having the hard mask layer opening; and filling the via opening and the hard mask layer opening with a metal to form a via in contact with the wiring line.

Abstract: An apparatus relating generally to a die stack is disclosed. In such an apparatus, a substrate is included. A first bond via array includes first wires each of a first length extending from a first surface of the substrate. An array of bump interconnects is disposed on the first surface. A die is interconnected to the substrate via the array of bump interconnects. A second bond via array includes second wires each of a second length different than the first length extending from a second surface of the die.

Abstract: In the semiconductor module according to the present invention, a conducting member which is used to electrically connect a semiconductor element arranged on a substrate or a bus bar with another electronic component is provided with a structure having flexibility capable of, in a junction with the semiconductor element, reducing the thermal stress due to difference in a coefficient of linear expansion between the conducting member and the semiconductor element, and absorbing dimensional error in objects to be connected. Therefore, the semiconductor module achieves both increased current capacity of the semiconductor device and improved reliability of the semiconductor module.

Abstract: A flexible environmental sensitive electronic device package including a flexible electronic device, a thin film encapsulation (TFE) and a sealing member is provided. The TFE covers the flexible electronic device as well as the sealing member covers the TFE and the flexible electronic device. The sealing member includes a first portion and a second portion, wherein the first portion covers the flexible electronic device and the TFE, and the second portion covers the first portion. Young's modulus of the second portion is between the 0 MPa and 100 MPa. Young's modulus of the first portion is greater than that of the second portion. The thickness of the first portion is less than that of the second portion.

Abstract: An electronic module including a semiconductor unit situated in a plastic housing, an electrically conductive plate system, via which the semiconductor unit may be supplied with electrical power, the electrically conductive plate system being connected in a planar fashion to a heat-generating integrated circuit of the semiconductor unit via a heat coupler; and the electrically conductive plate system being designed in such a way that it dissipates the heat generated by the heat-generating integrated circuit of the semiconductor unit to the plastic housing. A method for manufacturing a corresponding electronic module is also described.

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes a combination of tin and zinc that mitigates precipitation of residual copper by promoting the formation of miconstituents in the microbump. In another embodiment, the microbump has a mass fraction of zinc, or a mass fraction of tin, that is different in various regions along a height of the microbump.