Patents Examined by Alexander Sofocleous
  • Patent number: 10650900
    Abstract: A semiconductor memory device includes a first NAND string and a second NAND string sharing a channel and being connected in parallel. When reading a value from a first memory cell transistor of the first NAND string, a first potential is applied to a gate of a second memory cell transistor of the first NAND string and a gate of at least one of fourth memory cell transistors opposing the second memory cell transistor, a second potential is applied to a gate of a third memory cell transistor of the second NAND string opposing the first memory cell transistor, and a gate potential of the first memory cell transistor is swept between the second potential and the first potential. The second potential is lower than the first potential.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: May 12, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Shimada, Fumitaka Arai, Tatsuya Kato
  • Patent number: 10649689
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a first variable resistance element, a first switching element coupled to the first variable resistance element via a first line, a second variable resistance element, and a second switching element coupled to the second variable resistance element via a second line, wherein a distance between the first switching element and the first variable resistance element is larger than a distance between the second switching element and the second variable resistance element, and wherein a second path from a first terminal of the second switching element to the second variable resistance element includes a resistance component, a resistance of the second path being greater than a resistance of a first path, the first path being from a first terminal of the first switching element to the first variable resistance element.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 12, 2020
    Assignee: SK hynix Inc.
    Inventor: Nam-Kyun Park
  • Patent number: 10643711
    Abstract: Aspects relate to dynamically adapting the number of erase suspend operations on a non-volatile memory (NVM) based on the workload. In some aspects, erase suspend optimization involves computing a workload statistic based on at least read operations performed on the NVM over time, setting a maximum number of erase suspend operations allowed to be performed when the workload statistic compares favorably to a workload threshold, and preventing erase suspend operations from being performed when the workload statistic compares unfavorably to the workload threshold.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 5, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jingfeng Yuan, Xiaocheng Chen
  • Patent number: 10644030
    Abstract: An integrated circuit includes a substrate and a plurality of standard cells. The standard cells are formed on the substrate, wherein each standard cell comprises a first fin, a second fin and a third fin, the second fin is located between the first fin and the third fin, and there is a first interval between the first fin and the second fin is different from a second interval between the first fin and the third fin.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 5, 2020
    Assignee: MEDIATEK INC.
    Inventors: Chuan-Shian Fu, Cheng-Jyi Chang, Shao-Hwang Sher
  • Patent number: 10636495
    Abstract: Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Niang-Chu Chen, Jun Tao
  • Patent number: 10600472
    Abstract: Systems and methods are provided for implementing an array reset mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: March 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Huy T. Vo, Patrick Mullarkey, Jeffrey P. Wright, Michael A. Shore
  • Patent number: 10468108
    Abstract: Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sau Ching Wong
  • Patent number: 10468107
    Abstract: Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: November 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sau Ching Wong
  • Patent number: 10453521
    Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Yeop Baeck, Tae-Hyung Kim, Daeyoung Moon, Dong-Wook Seo, Inhak Lee, Hyunsu Choi, Taejoong Song, Jae-Seung Choi, Jung-Myung Kang, Hoon Kim, Jisu Yu, Sun-Yung Jang
  • Patent number: 10431307
    Abstract: An array organization and architecture for a content addressable memory (CAM) system. More specifically, a circuit is provided for that includes a first portion of the CAM configured to perform a first inequality operation implemented between 1 to n CAM entries. The circuit further includes a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries. The first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: October 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John E. Barth, Jr., Dean L. Lewis
  • Patent number: 10418116
    Abstract: A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes a plurality of memory blocks. The control logic groups the memory blocks, determines driving voltages to be respectively applied to the groups, and applies each of the determined driving voltages to memory blocks included in a corresponding group to control the operation of the memory cell array.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventors: Min Sang Park, Myoung Kwan Cho
  • Patent number: 10416210
    Abstract: A method for measuring a measurable flow of energy includes measuring, by ways of a measuring device belonging to a distribution network, a first “time-driven” or TDM measurement component obtained at predetermined time intervals, the first TDM measurement component including data related to physical parameters of said measurable flow of energy; measuring, by way of the measuring device, a second “event-driven” or EDM measurement component consolidated upon the occurrence of a significant change in at least one physical parameter of the flow of energy, the second EDM measurement component including data related to the physical parameters of the measurable flow of energy; combining the first TDM measurement component and the second EDM measurement component into a time sequence in order to control and manage an energy trend of the flow of energy in the distribution network in accordance with business logics.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: September 17, 2019
    Assignee: Fondazione Links—Leading Innovation & Knowledge for Society
    Inventor: Mikhail Simonov
  • Patent number: 10403389
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Patent number: 10395715
    Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Riccardo Muzzetto
  • Patent number: 10395705
    Abstract: An integrated circuit includes a substrate, a first circuit disposed on the substrate, a photoelectric cell disposed on the substrate and coupled to the first circuit, the photoelectric cell to provide power to the first circuit when the photoelectric cell is exposed to light, and the first circuit to allow disabling at least a portion of the integrated circuit when powered by the photoelectric cell.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: August 27, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Peter Rathfelder
  • Patent number: 10388334
    Abstract: An apparatus can include an array of memory cells coupled to sensing circuitry. The sensing circuitry can include a sense amplifier and a compute component. The sensing circuitry is to receive a scan vector and perform a scan chain operation on the scan vector. The sensing circuitry is controlled to write the resulting scan vector to a second portion of the array of memory cells.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Joshua E. Alzheimer, Debra M. Bell
  • Patent number: 10386806
    Abstract: A method for connecting models of technical systems in a testing device equipped for control unit development having a connection of a first model of a first technical system to a second model of a second technical system. The first model and the second model include a model of a control unit, a model of a technical system to be controlled, or a model of an environment interacting with the control unit or with the technical system to be controlled. The first model has a first data interface and the second model has a second data interface. The method has the provision of a first model hierarchy structure and the provision of a second model hierarchy structure. The method has an automatic configuration of compatible connections so that the first model present in the testing device exchanges data with the second model present in the testing device through compatible connections.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: August 20, 2019
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Marc Tegethoff
  • Patent number: 10381094
    Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i?1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i?1).
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: August 13, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chen-Jun Wu, Chih-Chang Hsieh, Tzu-Hsuan Hsu, Hang-Ting Lue
  • Patent number: 10379146
    Abstract: Methods, systems, and computer program products for detecting losses in electrical networks are provided herein. A computer-implemented method includes computing a consumption estimation for each consumer associated with a network; determining a difference between (i) the consumption estimation and (ii) actual consumption for each consumer; clustering the consumers into a cluster based on a consumption pattern associated with each consumer; determining a level of deviation of (i) the consumption pattern associated with each consumer from (ii) a consumption pattern representative of the cluster; clustering the consumers into two or more clusters based on a consumption pattern during a first interval of time and during a second interval of time; determining, for each consumer, a level of evolution from (i) a first cluster during the first interval to (ii) a second cluster during the second interval; and identifying consumers associated with a given loss within the network.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: August 13, 2019
    Assignees: International Business Machines Corporation, Universiti Brunei Darussalam
    Inventors: Sambaran Bandyopadhyay, Zainul Charbiwala, Tanuja Ganu, Pg Dr M. Iskandar Pg Hj Petra
  • Patent number: 10374152
    Abstract: Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junctions serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage, such that when the second field effect transistor of a selected magnetic tunnel junction is switched to direct the programming voltage to program the selected magnetic tunnel junction an unswitched magnetic tunnel junction and the second field effect transistor do not experience a voltage drop across the gates thereof sufficient to degrade.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, John K. DeBrosse, Chandrasekharan Kothandaraman