Patents Examined by Alexander Sofocleous
  • Patent number: 10418116
    Abstract: A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes a plurality of memory blocks. The control logic groups the memory blocks, determines driving voltages to be respectively applied to the groups, and applies each of the determined driving voltages to memory blocks included in a corresponding group to control the operation of the memory cell array.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventors: Min Sang Park, Myoung Kwan Cho
  • Patent number: 10416210
    Abstract: A method for measuring a measurable flow of energy includes measuring, by ways of a measuring device belonging to a distribution network, a first “time-driven” or TDM measurement component obtained at predetermined time intervals, the first TDM measurement component including data related to physical parameters of said measurable flow of energy; measuring, by way of the measuring device, a second “event-driven” or EDM measurement component consolidated upon the occurrence of a significant change in at least one physical parameter of the flow of energy, the second EDM measurement component including data related to the physical parameters of the measurable flow of energy; combining the first TDM measurement component and the second EDM measurement component into a time sequence in order to control and manage an energy trend of the flow of energy in the distribution network in accordance with business logics.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: September 17, 2019
    Assignee: Fondazione Links—Leading Innovation & Knowledge for Society
    Inventor: Mikhail Simonov
  • Patent number: 10403389
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Patent number: 10395715
    Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Riccardo Muzzetto
  • Patent number: 10395705
    Abstract: An integrated circuit includes a substrate, a first circuit disposed on the substrate, a photoelectric cell disposed on the substrate and coupled to the first circuit, the photoelectric cell to provide power to the first circuit when the photoelectric cell is exposed to light, and the first circuit to allow disabling at least a portion of the integrated circuit when powered by the photoelectric cell.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: August 27, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Peter Rathfelder
  • Patent number: 10388334
    Abstract: An apparatus can include an array of memory cells coupled to sensing circuitry. The sensing circuitry can include a sense amplifier and a compute component. The sensing circuitry is to receive a scan vector and perform a scan chain operation on the scan vector. The sensing circuitry is controlled to write the resulting scan vector to a second portion of the array of memory cells.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Joshua E. Alzheimer, Debra M. Bell
  • Patent number: 10386806
    Abstract: A method for connecting models of technical systems in a testing device equipped for control unit development having a connection of a first model of a first technical system to a second model of a second technical system. The first model and the second model include a model of a control unit, a model of a technical system to be controlled, or a model of an environment interacting with the control unit or with the technical system to be controlled. The first model has a first data interface and the second model has a second data interface. The method has the provision of a first model hierarchy structure and the provision of a second model hierarchy structure. The method has an automatic configuration of compatible connections so that the first model present in the testing device exchanges data with the second model present in the testing device through compatible connections.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: August 20, 2019
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventor: Marc Tegethoff
  • Patent number: 10379146
    Abstract: Methods, systems, and computer program products for detecting losses in electrical networks are provided herein. A computer-implemented method includes computing a consumption estimation for each consumer associated with a network; determining a difference between (i) the consumption estimation and (ii) actual consumption for each consumer; clustering the consumers into a cluster based on a consumption pattern associated with each consumer; determining a level of deviation of (i) the consumption pattern associated with each consumer from (ii) a consumption pattern representative of the cluster; clustering the consumers into two or more clusters based on a consumption pattern during a first interval of time and during a second interval of time; determining, for each consumer, a level of evolution from (i) a first cluster during the first interval to (ii) a second cluster during the second interval; and identifying consumers associated with a given loss within the network.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: August 13, 2019
    Assignees: International Business Machines Corporation, Universiti Brunei Darussalam
    Inventors: Sambaran Bandyopadhyay, Zainul Charbiwala, Tanuja Ganu, Pg Dr M. Iskandar Pg Hj Petra
  • Patent number: 10381094
    Abstract: A two-sided, staged programming operation is applied to a memory having first and second stacks of memory cells C1(i) and C2(i), i being the physical level of a cell. The staged programming operation includes applying a preliminary program stage S1, an intermediate program stage S2, and a final program stage S3 to memory cells in the first and second stacks. In a programming order the final program stage S3 is applied to memory cells in the first and second stacks at each level (i) for which the intermediate program stage S2 has already been applied to the memory cells in any neighboring levels (levels i+1 and i?1). The intermediate program stage S2 is applied only to memory cells for which the preliminary program stage S1 has already been applied to the cells in any neighboring levels (levels i+1 and i?1).
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: August 13, 2019
    Inventors: Chen-Jun Wu, Chih-Chang Hsieh, Tzu-Hsuan Hsu, Hang-Ting Lue
  • Patent number: 10374152
    Abstract: Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junctions serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage, such that when the second field effect transistor of a selected magnetic tunnel junction is switched to direct the programming voltage to program the selected magnetic tunnel junction an unswitched magnetic tunnel junction and the second field effect transistor do not experience a voltage drop across the gates thereof sufficient to degrade.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 6, 2019
    Inventors: Anthony J. Annunziata, John K. DeBrosse, Chandrasekharan Kothandaraman
  • Patent number: 10360972
    Abstract: A memory system includes dynamic random-access memory (DRAM) component that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: July 23, 2019
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, John Eric Linstadt, Thomas J. Giovannini, Scott C. Best, Kenneth L. Wright
  • Patent number: 10338146
    Abstract: In order to create a control observer for any battery type in a structured and at least partially automated manner, first, a nonlinear model of the battery, in form of a local model network including a number of local, linear, time-invariant, and dynamic models, which each have validity in specific ranges of the input variables, is determined from the measuring data of a previously ascertained, optimized experimental design via a data-based modeling method. For each local model (LMi) of the model network determined in this manner, a local observer is then determined. The control observer (13) for estimating the SoC then results from a linear combination of the local observers.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: July 2, 2019
    Assignee: AVL List GmbH
    Inventors: Christoph Hametner, Stefan Jakubek, Amra Suljanovic
  • Patent number: 10338831
    Abstract: Present disclosure includes a system for preserving data in a volatile memory and a method thereof. The volatile memory comprises a plurality of refreshing units, and each of the refreshing units comprises a plurality of word lines for storing data. The system comprises an accessing unit. The accessing unit is configured to detect a row-hammer indication indicating a first word line is frequently accessed, wherein the accessing unit is configured to copy data stored in the first word line to a second word line when the row-hammer indication is detected on the first word line, wherein the data stored in the first and the second word lines are available to be selectively accessed.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 2, 2019
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10337930
    Abstract: A number of variations may include a method which may include determining a temperature rise in an IGBT junction without the use of a temperature estimation or measurement device because determination may be made by first determining the power loss due to the conduction losses of the IGBT and power loss associated with switching the IGBT where these losses may be determined by utilizing the saturation voltage of the IGBT, IGBT PWM duty cycle, IGBT switching frequency, fundamental frequency along with a lookup table for the switching energies and the phase current going through the IGBT. The determined power loss may be multiplied by a measured, sensed or obtained thermal impedance from the IGBT junction. Finally, the determined temperature rise of the IGBT junction may be added to a measured, sensed or obtained temperature of the coolant in order to determine the absolute temperature of the IGBT junction.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: July 2, 2019
    Inventors: S. M. Nayeem Hasan, Bryan M. Ludwig, David P. Tasky
  • Patent number: 10319431
    Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 11, 2019
    Inventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
  • Patent number: 10319422
    Abstract: A decoder according to one embodiment of the invention includes a set of lines, a resonator circuit, a set of input leads for receiving input signals, and a set of switches for coupling some of the lines within the set of lines to the resonator circuit in response to the input signals while the other lines within the set of lines are at a first binary voltage. The lines are coupled to a set of pointer circuits. The pointer circuits perform logic functions on the signals on the lines when the resonating signal is at a second binary voltage opposite the first binary voltage to thereby decode the input signals. Because the lines are driven high and low by a resonator circuit, the decoder circuit power consumption is less than it would be if the lines were pulled up and down by a set of pullup and pulldown transistors.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 11, 2019
    Inventor: David A. Huffman
  • Patent number: 10312248
    Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 4, 2019
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
  • Patent number: 10304519
    Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: May 28, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Troy A. Manning
  • Patent number: 10283181
    Abstract: Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: May 7, 2019
    Inventor: David J. Toops
  • Patent number: 10276222
    Abstract: In accordance with one embodiment, a method for accessing a memory is provided, including carrying out a first access to the memory and charging, for a memory cell, a bit line coupled to the memory cell to a value which is stored or to be stored in the memory cell, holding the state of the bit line until a second access, which follows the first access, and outputting the held state if the second access is a read access to the memory cell.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: April 30, 2019
    Inventors: Thomas Kuenemund, Gerd Dirscherl, Gunther Fenzl, Joel Hatsch, Nikolai Sefzik