Abstract: Methods, systems, and devices related to row activation indication registers are disclosed. A first register can be coupled to a memory device and configured to store an indication of a first number of bit locations of a row address corresponding to the memory device to use in association with optimization of a row precharge time (tRP) of the memory device. A second register can be coupled to the memory device and configured to store an indication of a second number of bit locations of the row address to use in association with optimization of a row address to column address delay (tRCD) of the memory device.

Abstract: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell and a second memory cell arranged adjacent to each other and coupled in series; and a control circuit, wherein the control circuit is configured to: at a time of the program operation in a first program loop operation targeted for the first memory cell, during a first period, while suppling a first write voltage to the first memory cell, supply a first voltage smaller than the first write voltage to the second memory cell, and during a second period, while supplying a second voltage smaller than the first voltage to the first memory cell, supply a third voltage greater than the second voltage to the second memory cell.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell; a word line coupled to a gate of the first memory cell; a first transistor having a first end coupled to the word line; and a control circuit configured to, in a read operation, apply a first voltage, which is positive, to a back gate of the first transistor.

Abstract: A sense amplifier control system includes a precharge control switch configured to receive a precharge signal. A reference cell is configured to receive a reference word line signal. In a precharge phase, the control switch is controlled in response to the precharge signal to precharge the reference input node to a predetermined precharge level. In a sensing phase subsequent to the pre-charge phase, the trigger circuit is configured to output a triggering signal at the output terminal in response to the reference input node reaching a triggering level.

Abstract: In a semiconductor memory device, an n-type semiconductor layer is formed on a p-type semiconductor region on a substrate, a p-type first semiconductor layer having a columnar shape and concave top surface extends vertically from part of the n-type semiconductor layer, the p-type first semiconductor layer and n-type semiconductor layer are partially covered with an insulating layer, a first gate insulating layer is placed in contact with the p-type first semiconductor layer, a first gate conductor layer is placed in contact with the first gate insulating layer, and a second gate insulating layer, a second gate conductor layer, and an access transistor with an n+ layer provided on both sides are installed along a surface of the p-type first semiconductor layer.

Abstract: Interfaces between higher voltage and lower voltage wafers and related apparatuses and methods are disclosed. An apparatus includes a memory wafer and a logic wafer. Data storage elements of an array are configured to perform an operation responsive to an operational voltage potential. The memory wafer also includes bitlines electrically connected to the data storage elements and isolation devices electrically connected to the bitlines. The logic wafer is bonded to the memory wafer. The logic wafer includes logic circuitry electrically connected to the bitlines through the isolation devices. A maximum voltage potential difference tolerance of the logic circuitry is less than an operational voltage potential difference between the operational voltage potential and a reference voltage potential of the logic circuitry.

Abstract: Control logic in a memory device initiates a program operation to program one or more memory cells of a first sub-block of a memory array, the program operation including a seeding phase. During the seeding phase, a first wordline voltage is caused to be applied to a first wordline segment associated with a first portion of the memory array. During the seeding phase, a second wordline voltage is caused to be applied to a second wordline segment associated with a second portion of the memory array, where the first wordline voltage and the second wordline voltage cause a seeding bias voltage to be applied to the first sub-block group and inhibit application of the seeding bias voltage to the second sub-block group.

Abstract: According to an embodiment of the present disclosure, a memory device includes a memory cell array including a plurality of planes; a charge pump configured to generate an operating voltage used for an operation on each of the plurality of planes according to a first clock signal having a first cycle; page buffers each configured to store pass data representing whether an operation of each of the plurality of planes has been completed; and an operation control circuit configured to, based on a number of the pass data received from the page buffers, control the charge pump to generate the operating voltage according to a second clock signal having a second cycle that is longer than the first cycle.

Abstract: A memory device, and a method of operating the memory device, includes a memory block, a peripheral circuit, an erase controller, and a parameter setter. The memory device includes a plurality of sub blocks. The peripheral circuit performs an erase operation on a target sub block among the plurality of sub blocks. The erase controller controls the peripheral circuit to perform the erase operation based on a default parameter or an optimal parameter according to a group to which the target sub block belongs among first, second, and third groups. The parameter setter sets the optimal parameter based on a result of the erase operation when the target sub block is included in the first group or the third group.

Abstract: An address counter comprises a flip-flop for performing a load operation of loading a start column address signal, responsive to a first logic signal provided to the flip-flop SET terminal and a second logic signal provided to a RESET terminal and for performing a counting operation of sequentially increasing a data value of the start column address signal.

Abstract: The present disclosure provides memory devices, operating methods thereof, memory systems, and word line voltage control circuits. A disclosed memory device comprises an array of memory cells, a plurality of word lines coupled with the memory cells, and a peripheral circuit coupled to the memory cells through the word lines. The peripheral circuit is configured to reduce a first voltage on a non-selected word line adjacent to a selected word line to a second voltage, provide a pre-charge voltage to the selected word line, increase the second voltage on the non-selected word line to a third voltage, and float the selected word line.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: A memory circuit includes a plurality of first memory cells. The plurality of first memory cells are operatively coupled to a first bit line. The memory circuit further includes a first pre-charge circuit connected to a first end of the first bit line and configured to charge the first bit line to a supply voltage during a first time period prior to any of the first memory cells being accessed. The memory circuit further includes a second pre-charge circuit connected to a second end of the first bit line and also configured to charge the first bit line to the supply voltage during the first time period. The second pre-charge circuit is only activated during a second time period at a beginning of the first time period, while the first pre-charge circuit is activated during a whole of the first time period.

Abstract: A memory device may include a level shifter circuit that drives multiples half latch circuits. The half latch circuits may each include a p-channel transistor whose source is connected to a first voltage and whose gate is to receive addressing signals, a first inverter circuit connected between the drain of the p-channel transistor and a second voltage and whose input is connected to an output of the level shifter circuit, a second inverter circuit connected between the second voltage and a third voltage to receive an output of the first inverter circuit as input, a third inverter circuit connected between the second and third voltages to receive an output of the second inverter circuit as input, and an n-channel transistor connected between the output of the third inverter circuit and the input of the second inverter circuit, wherein a gate of the n-channel transistor is connected to a bias voltage.

Abstract: Technology is disclosed herein for programing memory cells with a post-program erase. In an aspect, the post-program erase includes a bit-level erase that only erases memory cells that are to remain in an erased state after the program operation. Memory cells that are to remain in programmed states may be inhibited from erase during the post-program erase. In an aspect, the post-program erase does not have an erase verify, which saves time and/or power. In an aspect, the post-program erase includes applying a single erase pulse, which saves time and/or power. In an aspect, the duration of the post-program erase pulse is shorter than an erase pulse used prior to programming, which saves time and/or power.

Abstract: An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1?0) ST CLK # based on PCLK assertion (0?1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.

Abstract: An apparatus includes control circuits configured to connect to a plurality of nonvolatile memory cells. The one or more control circuits are configured to apply read voltages on a plurality of word lines connected to the nonvolatile memory cells, ramp down from the read voltages to subsequent voltages such that voltage on a word line transitions through a voltage that is below a subsequent voltage by a negative kick voltage. The one or more control circuits are further configured to apply a first negative kick voltage to ramp down from a read voltage on a first word line and apply a second negative kick voltage to ramp down from the read voltage on a second word line.

Abstract: A memory device, comprising: a memory cell array including a plurality of memory cell strings, and coupled between a plurality of bit lines and a plurality of word lines, the bit lines commonly coupled to a common source line, and a control portion suitable for: precharging the bit lines to a first level during a read operation for selected memory cells coupled to a selected word line of the word lines, and precharging the bit lines to a second level during a verify operation of a program operation for the selected memory cells, wherein the second level is lower than the first level by a set level.

Abstract: A processing device, operatively coupled with a memory device, receives a request to perform a programming operation on a first set of a block addressable by a first wordline of a first die of the memory device, wherein the first die comprises a plurality of decks of the memory device. The processing device identifies, based on a predefined usage type associated with the first die, a deck of the plurality of decks for performing the programming operation; and performing the programming operation on a second set of cells of the block addressable by the first wordline residing on the identified deck of the first die.