Abstract: A memory device, and a method of operating the memory device, includes a memory block, a peripheral circuit, an erase controller, and a parameter setter. The memory device includes a plurality of sub blocks. The peripheral circuit performs an erase operation on a target sub block among the plurality of sub blocks. The erase controller controls the peripheral circuit to perform the erase operation based on a default parameter or an optimal parameter according to a group to which the target sub block belongs among first, second, and third groups. The parameter setter sets the optimal parameter based on a result of the erase operation when the target sub block is included in the first group or the third group.

Abstract: An address counter comprises a flip-flop for performing a load operation of loading a start column address signal, responsive to a first logic signal provided to the flip-flop SET terminal and a second logic signal provided to a RESET terminal and for performing a counting operation of sequentially increasing a data value of the start column address signal.

Abstract: The present disclosure provides memory devices, operating methods thereof, memory systems, and word line voltage control circuits. A disclosed memory device comprises an array of memory cells, a plurality of word lines coupled with the memory cells, and a peripheral circuit coupled to the memory cells through the word lines. The peripheral circuit is configured to reduce a first voltage on a non-selected word line adjacent to a selected word line to a second voltage, provide a pre-charge voltage to the selected word line, increase the second voltage on the non-selected word line to a third voltage, and float the selected word line.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: A memory circuit includes a plurality of first memory cells. The plurality of first memory cells are operatively coupled to a first bit line. The memory circuit further includes a first pre-charge circuit connected to a first end of the first bit line and configured to charge the first bit line to a supply voltage during a first time period prior to any of the first memory cells being accessed. The memory circuit further includes a second pre-charge circuit connected to a second end of the first bit line and also configured to charge the first bit line to the supply voltage during the first time period. The second pre-charge circuit is only activated during a second time period at a beginning of the first time period, while the first pre-charge circuit is activated during a whole of the first time period.

Abstract: A memory device may include a level shifter circuit that drives multiples half latch circuits. The half latch circuits may each include a p-channel transistor whose source is connected to a first voltage and whose gate is to receive addressing signals, a first inverter circuit connected between the drain of the p-channel transistor and a second voltage and whose input is connected to an output of the level shifter circuit, a second inverter circuit connected between the second voltage and a third voltage to receive an output of the first inverter circuit as input, a third inverter circuit connected between the second and third voltages to receive an output of the second inverter circuit as input, and an n-channel transistor connected between the output of the third inverter circuit and the input of the second inverter circuit, wherein a gate of the n-channel transistor is connected to a bias voltage.

Abstract: Technology is disclosed herein for programing memory cells with a post-program erase. In an aspect, the post-program erase includes a bit-level erase that only erases memory cells that are to remain in an erased state after the program operation. Memory cells that are to remain in programmed states may be inhibited from erase during the post-program erase. In an aspect, the post-program erase does not have an erase verify, which saves time and/or power. In an aspect, the post-program erase includes applying a single erase pulse, which saves time and/or power. In an aspect, the duration of the post-program erase pulse is shorter than an erase pulse used prior to programming, which saves time and/or power.

Abstract: An apparatus, system, and method for improved clock generator circuit operation. A self-resetting clock generator circuit includes a keeper-free clock gate configured to generate a stabilized positive clock (PCLK) signal based on an enable (ENBL) signal, a positive clock (PCLK), a reset (RST) signal, and an external clock (SOC CLK), a first bank of transistors configured to assert a clock signal (ST CLK) based on PCLK, a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1?0) ST CLK # based on PCLK assertion (0?1), and a logic gate-based reset circuit configured to generate the RST signal based on the SOC CLK and the ST CLK #.

Abstract: An apparatus includes control circuits configured to connect to a plurality of nonvolatile memory cells. The one or more control circuits are configured to apply read voltages on a plurality of word lines connected to the nonvolatile memory cells, ramp down from the read voltages to subsequent voltages such that voltage on a word line transitions through a voltage that is below a subsequent voltage by a negative kick voltage. The one or more control circuits are further configured to apply a first negative kick voltage to ramp down from a read voltage on a first word line and apply a second negative kick voltage to ramp down from the read voltage on a second word line.

Abstract: A memory device, comprising: a memory cell array including a plurality of memory cell strings, and coupled between a plurality of bit lines and a plurality of word lines, the bit lines commonly coupled to a common source line, and a control portion suitable for: precharging the bit lines to a first level during a read operation for selected memory cells coupled to a selected word line of the word lines, and precharging the bit lines to a second level during a verify operation of a program operation for the selected memory cells, wherein the second level is lower than the first level by a set level.

Abstract: A processing device, operatively coupled with a memory device, receives a request to perform a programming operation on a first set of a block addressable by a first wordline of a first die of the memory device, wherein the first die comprises a plurality of decks of the memory device. The processing device identifies, based on a predefined usage type associated with the first die, a deck of the plurality of decks for performing the programming operation; and performing the programming operation on a second set of cells of the block addressable by the first wordline residing on the identified deck of the first die.

Abstract: Technology for gate induced drain leakage (GIDL) erase of NAND strings. The drain-to-gate voltage of a source side select transistor (or transistors) is trimmed to compensate for different physical characteristics of the NAND strings in different regions of a memory system. The drain-to-gate voltage generates a GIDL current at the source end of a NAND string during a GIDL erase. The memory system uses different magnitudes for the drain-to-gate voltage applied to source side select transistor(s) on NAND strings in different regions of the memory system to provide for more uniform GIDL current during erase.

Abstract: Technology is disclosed herein for a storage system and method for multi-stage discharge of a read pass voltage. In an aspect, the voltage on unselected word lines is reduced from the read pass voltage to an intermediate voltage during a first stage near the end of a read operation. A read reference voltage on the selected word line may be changed (e.g., increased) to the intermediate voltage during the first stage. During a second stage the voltage on the unselected word lines may be reduced from the intermediate voltage to a final voltage. The voltage on the selected word line may also be decreased during the second stage from the intermediate voltage to the final voltage. The multi-stage discharge of the read pass voltage may reduce peak current consumption (e.g., peak Icc) in a final portion of the read operation.

Abstract: Example memory devices, memory systems, methods, and media for detection of leakage current in a memory device are disclosed. One example method includes performing a program operation of the memory device. A voltage over a combination of one or more resistors is compared with a preset threshold during the program operation, where the one or more resistors are positioned between a pump source and a global word line in the memory device. It is determined that the voltage is larger than or equal to the preset threshold. In response to the determination that the voltage is larger than or equal to the preset threshold, it is indicated that a leakage current exist in a word line coupled to a memory cell in the memory device.

Abstract: A memory device includes a memory cell array, a control logic which controls a read operation to read hard decision data and soft decision data from each page, and a page buffer which includes a first latch related to sensing of the hard decision data and a second latch related to sensing of the soft decision data. The control logic controls performing a first sensing operation of storing a value determined based on a first offset level, in the second latch, at a first sensing timing, and a second sensing operation of storing a value determined based on a second offset level, in the second latch, at a second sensing timing, and performs a control operation to provide a set signal SET to the second latch in the first sensing operation, and provide a reset signal RST to the second latch in the second sensing operation.

Abstract: According to an embodiment, a semiconductor memory device includes a first chip, a second chip, and a third chip. The third chip is connected to the first chip via a first channel and connected to the second chip via a second channel. Upon receiving a first command sequence for data transfer from a first device, the third chip transfers a second command sequence for the data transfer to the first chip via the first channel and transfers a third command sequence for the data transfer to the second chip via the second channel. The first address includes a chip identification number of a value indicating the first chip. The second command sequence includes the first address. The third command sequence includes a second address obtained by replacing the value of the chip identification number in the first address indicating the first chip to a value indicating the second chip.

Abstract: Provided is a memory system including a memory module bank comprising a plurality of memory cell arrays, each memory cell array comprising a plurality of memory cells arranged in wordlines and bitlines and a memory controller configured to receive from a central processing unit (CPU) a data byte to be stored in a wordline of the memory module bank. Also included is a logical-to-physical address mapping block (L2P AMB) configured to map a logical bitline address of the data byte to a physical bitline address of a first memory cell array of the plurality of memory cell arrays, wherein a plurality of logical bitline addresses of the data byte are shuffled to different physical bitline memory addresses of the first memory cell array. Each respective memory cell array of the plurality stores a respective bit value, corresponding to a common logical bitline address, to a different respective physical bitline in each different respective memory cell array of the plurality.

Abstract: A compute-in-memory array is provided that implements a filter for a layer in a neural network. The filter multiplies a plurality of activation bits by a plurality of filter weight bits for each channel in a plurality of channels through a charge accumulation from a plurality of capacitors. The accumulated charge is digitized to provide the output of the filter.

Abstract: A memory system includes a first controller, a nonvolatile memory connected to the first controller, and a power supply circuit that applies a voltage to the first controller and the nonvolatile memory. The first controller writes first data to a first address in the nonvolatile memory and instructs the power supply circuit to apply the destruction voltage to the nonvolatile memory. The first controller determines whether the first data can be correctly read from the first address in the nonvolatile memory and checks destruction of the nonvolatile memory based on the determination.

Abstract: A memory device is provided. The memory device comprises a memory cell, a first power rail and a suppressing circuit. The memory cell is coupled to a word line. The first power rail transmits a first supply voltage. The suppressing circuit comprises a first transistor and a second transistor. The first transistor is diode-connected, coupled to the word line, and disposed at a first layer. The second transistor is diode-connected coupled between the first transistor and the first power rail, and disposed at a second layer under the first layer. The first transistor and the second transistor overlap with each other in a layout view.