Abstract: A memory device and associated operation method are provided. The operation method is applied to the memory device to determine whether a search input and in-memory data are matched. The memory device includes a memory array and a control circuit, and the memory array includes M*N memory cells. The operation method includes the following steps. A select voltage is applied to an n-th word line. A pass-through voltage is applied to (N?1) word lines. A first search voltage is applied to an m-th first bit-line, and a second search voltage is applied to an m-th second bit-line. An m-th first sensing current and an m-th second sensing current bit are selectively generated. Then, a sensing circuit in the control circuit generates a sensing circuit output. The sensing circuit output represents whether the m-th first sensing current and the m-th second sensing current are generated.

Abstract: A method includes training a timing flip-flop circuit positioned between a controller and a memory resource, providing a plurality of data signals and a plurality of clock signals to the timing flip-flop circuit to generate a plurality of output clock signals and a plurality of output data signals, serializing the plurality of output clock signals and the plurality of output data signals, and providing the serialized plurality of output clock signals and the serialized plurality of output data signals to one of the controllers or the memory resources.

Abstract: The present disclosure provides a three-dimensional NAND memory device, comprising a memory array comprising blocks, each block includes first memory cells and second memory cells connected in series to a bit line, a word line driver, and a controller configured to control the word line driver to: performing a programming operation on a memory cell in the first memory cells, the memory cell is controlled by a selected word line of first word lines corresponding to the first memory cells, the first word lines comprising first unselected word lines adjacent to the selected word line, and the performing the programming operation comprises: applying a programming voltage signal to the selected word line to program the memory cell into a target state; applying a first pass voltage to the first unselected word lines; and applying a second pass voltage to second word lines corresponding to the second memory cells.

Abstract: The memory device includes a memory block with an array of memory cells. The memory cells are arranged in a plurality of word lines and in a plurality of memory holes. The plurality of memory holes are in electrical communication with respective bit lines of a plurality of bit lines. The plurality of bit lines includes a plurality of active bit lines and a plurality of inactive bit lines. The active bit lines are in electrical communication with active sense amplifiers and memory cells during read operations, and the inactive bit lines are not in electrical communication with active sense amplifiers or memory cells during the read operations.

Abstract: A page buffer of a semiconductor memory device includes a bit line connection transistor, an internal operation circuit, and a plurality of latch circuits. During a program operation of selected memory cells, a power voltage is applied to the bit line connection transistor to set a voltage of a bit line connected to memory cells having a threshold voltage greater than a main verify voltage as a program inhibit voltage. In addition, a second program allowable voltage less than the program inhibit voltage is applied to the bit line connection transistor. In addition, a first program allowable voltage less than the second program allowable voltage is applied to the gate of the bit line connection transistor.

Abstract: Examples of the present application disclose a memory device. The memory device includes: a memory cell array comprising memory cells that store a plurality of memory bits, the plurality of memory bits corresponding to a plurality of orders of read voltages, and a preset number of the memory cells forming a code word; and a peripheral circuit coupled with the memory cell array and configured to: acquire a first result of at least one code word corresponding to a target read voltage of a target order; acquire a predicted valley bottom voltage of the target order according to the first result of the at least one code word corresponding to the target read voltage of the target order and a level in which the target order is located; and determine a target valley bottom voltage of the target order based on the predicted valley bottom voltage of the target order.

Abstract: A device structure includes base semiconductor rail structures overlying a semiconductor substrate, bottom bit lines contacting a sidewall of a respective one of the base semiconductor rail structures, a two-dimensional array of lower semiconductor pillars, lower gate electrode lines overlying the bottom bit lines and laterally spaced from sidewall segments of a respective column of the lower semiconductor pillars by a lower gate dielectric layer, a two-dimensional array of upper semiconductor pillars, upper gate electrode lines overlying the lower gate electrode lines and laterally spaced from sidewall segments of a respective column of the upper semiconductor pillars by an upper gate dielectric layer, and at least one top bit line contacting top surfaces of a respective row of upper semiconductor pillars.

Abstract: Provided is a magnetic storage device 10 comprising: a magnetoresistive element 11 having a structure in which a recording layer 13 that includes a first magnetic layer, a tunnel barrier layer 14, and a reference layer 15 that includes a second magnetic layer are laminated; and a control unit 12, wherein the in-plane shape of the recording layer 13 is such that a rectangle circumscribing the in-plane shape and having the smallest area has a short side and a long side which have mutually different lengths, and at the time of writing to the recording layer 13, the control unit 12 applies a voltage pulse to the magnetoresistive element 11 while applying an effective magnetic field in the direction of the short side in the plane of the recording layer 13.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read the first logical page to obtain first readout information, second readout information and third readout information, respectively; selecting a second logical page of the physical page; using a second set of threshold voltage to read the second logical page to generate fourth readout information; adjusting the first set of threshold voltages to generate an adjusted first set of threshold voltages according to the first readout information, the second readout information, the third readout information and the fourth readout information; and using the adjusted first set of threshold voltages to read the first logical page of the flash memory module.

Abstract: A training method of a memory device adjusting an eye window of a data signal in response to a duty cycle adjuster (DCA) includes performing a first training operation that selects a first DCA code corresponding to a first internal clock signal having a phase difference of 180° relative to a reference internal clock signal, and performing a second training operation that selects a second DCA code and a third DCA code respectively corresponding to a second internal clock signal and a third internal clock signal having a phase difference of 90° and 270° relative to reference internal clock signal. In the first training operation, the eye window size of the data signal is measured in units of two unit intervals, and in the second training operation, the eye window size of the data signal is measured in units of one unit interval.

Abstract: To reduce the time required for data writing. A semiconductor memory device is provided, comprising a memory cell having a gate electrode including a selection gate and a memory gate, a source line connected to a source, and a bit line connected to a drain, an extraction part that extracts a current flowing from the source side to the drain side during writing in the memory cell from the bit line, a discharge part that has a higher ability to pass current than the extraction part and lowers the voltage of the bit line, a charge part that has a higher ability to pass current than the discharge part and applies a voltage to the bit line, and a control part that, when starting to write to the memory cell, lowers the voltage of the bit line by the discharge part and applies a voltage to the bit line by the charge part.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of memory strings, a peripheral circuit configured to perform an erase operation and a program operation on the memory block, and a control logic configured to control the peripheral circuit to perform the erase operation and the program operation on the memory block, wherein the control logic is configured to control the peripheral circuit to perform an abnormally injected electron removal operation that removes abnormally injected electrons trapped in a charge storage layer of a plurality of memory cells included in the memory block after the erase operation has been completed.

Abstract: Technology for operating word line switch transistors in a memory system. A memory system provides for separate control of the voltage to the gates of the word line switch transistors and a voltage to a well in which the word line switch transistors reside. This allows for a negative voltage to be applied to the gates and/or the well. However, if desired, a non-negative voltage (e.g., 0V) may be applied to the gates or the well.

Abstract: An operating method of a memory system is disclosed herein. The operating method includes: inputting tracking data to a tracking array; generating tracking logic values by tracking cell columns of the tracking array according to the tracking data; counting the tracking logic values to generate a summation value; adjusting a sensing time of a sensing device according to the summation value; performing a computing operation by a computing array to generate computing signals; and sensing the computing signals by the sensing device according to the adjusted sensing time.

Abstract: A non-volatile memory device comprises an array of non-volatile memory cells, a controller in communication with the non-volatile memory cell, a row driver including a plurality of high-voltage switches for applying high-voltages to non-volatile memory cells, a column driver including a plurality of sensing circuits for monitoring the data of the non-volatile memory cells; and, a plurality of time delay circuits, wherein the time delay circuit is configured to reduce peak current caused by simultaneous application of high voltages to the non-volatile memory cells or simultaneous detection of current flowing across bit lines of the non-volatile memory cells.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to program the memory cells in a program operation. During the program operation, the control means programs the memory cells connected to at least one particular word line of the plurality of word lines using a first programming technique while programming the memory cells connected to plurality of word lines other than the at least one particular word line using a second programming technique different than the first programming technique.

Abstract: Methods, systems, and devices related to row activation indication registers are disclosed. A first register can be coupled to a memory device and configured to store an indication of a first number of bit locations of a row address corresponding to the memory device to use in association with optimization of a row precharge time (tRP) of the memory device. A second register can be coupled to the memory device and configured to store an indication of a second number of bit locations of the row address to use in association with optimization of a row address to column address delay (tRCD) of the memory device.

Abstract: In a method of operating one or more nonvolatile memory devices including one or more memory blocks, each memory block includes a plurality of memory cells and a plurality of pages arranged in a vertical direction. Pages arranged in a first direction of a channel hole are set as first to N-th pages. A size of the channel hole increases in the first direction and decreases in the second direction. Pages arranged in a second direction of the channel hole are set as (N+1)-th to 2N-th pages. First to N-th page pairs are set such that a K-th page among the first to the N-th pages and an (N+K)-th page among the (N+1)-th to 2N-th pages form one page pair. Parity regions of two pages included in at least one page pair are shared by the two pages included in the at least one page pair.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell and a second memory cell arranged adjacent to each other and coupled in series; and a control circuit, wherein the control circuit is configured to: at a time of the program operation in a first program loop operation targeted for the first memory cell, during a first period, while suppling a first write voltage to the first memory cell, supply a first voltage smaller than the first write voltage to the second memory cell, and during a second period, while supplying a second voltage smaller than the first voltage to the first memory cell, supply a third voltage greater than the second voltage to the second memory cell.

Abstract: According to one embodiment, a semiconductor memory device includes a first memory cell; a word line coupled to a gate of the first memory cell; a first transistor having a first end coupled to the word line; and a control circuit configured to, in a read operation, apply a first voltage, which is positive, to a back gate of the first transistor.