Patents Examined by Alexander Sofocleous
  • Patent number: 10014060
    Abstract: A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of memory and a controller. The controller is configured to detect a read disturb error in a block, identify data that caused the read disturb error, and move the data that caused the read disturb error to a block with a higher read endurance. This can be done by assigning read counters to blocks to determine frequently-read data, and storing that data in a separate block until it is less frequently read and will likely not cause additional read disturb errors.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: July 3, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel E. Tuers, Abhijeet Manohar, Nicholas Thomas, Jonathan Hsu
  • Patent number: 10014070
    Abstract: Methods and memories for verifying data path integrity are provided. In one such method, a first set of data are read from a first register of a memory device while a second set of data are written to an array of the memory device. The read first set of data and the data written to the first register are compared to verify data path integrity.
    Type: Grant
    Filed: June 17, 2013
    Date of Patent: July 3, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Terry Grunzke
  • Patent number: 10008265
    Abstract: A memory system is configured to store information using a hybrid volatile and nonvolatile memory device. The memory system, in one aspect, includes memory components, a drain select gate (“DSG”) transistor, and a capacitor component. Each memory component, in one example, includes a source terminal, a gate terminal, a drain terminal, and a nonvolatile cell. The memory components are organized in a string formation and the components are interconnected between source terminals and drain terminals. The drain terminal of DSG transistor is coupled to the source terminal of a memory component and the gate terminal of DSG transistor is coupled to a DSG signal. The drain terminal of the capacitor is coupled to the source terminal of the first DSG transistor. The capacitor component is configured to perform a dynamic random-access memory (“DRAM”) function.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: June 26, 2018
    Assignee: NEO Semiconductor, Inc.
    Inventor: Fu-Chang Hsu
  • Patent number: 10002931
    Abstract: A silicon carbide semiconductor device capable of effectively increasing a threshold voltage and a method for manufacturing the silicon carbide semiconductor device. The silicon carbide semiconductor device includes a gate insulating film formed on part of surfaces of the well regions and the source region; and a gate electrode formed on a surface of the gate insulating film so as to be opposite to an end portion of the source region and the well regions. Furthermore, the gate insulating film has, in an interface region between the well regions and the gate insulating film, defects that each form a first trap having an energy level deeper than a conduction band end of silicon carbide and that include a bond between silicon and hydrogen.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: June 19, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Masayuki Furuhashi, Naruhisa Miura
  • Patent number: 10002664
    Abstract: The invention more particularly relates to a resistive memory cell comprising a first and a second metal electrodes and a solid electrolyte positioned between the first and the second metal electrodes, with the solid electrolyte comprising a commutation layer in contact with the first electrode and a dielectric layer, with said resistive memory cell being able to be electrically modified so as to switch from a first resistive state to a second resistive state (state LRS) wherein the resistance (RON) of the memory cell is at least ten times smaller than the resistance (ROFF) of the memory cell in the HRS state, in the LRS state the first electrode being so arranged as to supply metal ions intended to form at least a conductive filament through said commutation layer, with the cell being characterized in that, in the LRS state, the memory cell is conductive for a range of voltages between 0 Volts and VREST 2 .
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: June 19, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Elisa Vianello, Gabriel Molas, Giorgio Palma, Olivier Thomas
  • Patent number: 9997594
    Abstract: A compound semiconductor device includes: a GaN-based channel layer; a barrier layer of nitride semiconductor above the channel layer; and a cap layer of nitride semiconductor above the barrier layer, wherein the cap layer includes: a first region doped with Fe; and a second region above the first region, a concentration of Fe in the second region being lower than a concentration of Fe in the first region.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: June 12, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura
  • Patent number: 9990988
    Abstract: A determination can be made as to whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: June 5, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Robert B. Eisenhuth
  • Patent number: 9984742
    Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: May 29, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
  • Patent number: 9978665
    Abstract: A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A semiconductor component is disposed over the semiconductor die. The semiconductor component includes a second interconnect structure. The semiconductor component is disposed over the semiconductor die to align the second interconnect structure with the first interconnect structure. The first interconnect structure includes a plurality of interconnection units disposed around first and second adjacent sides of the semiconductor die to form an L-shape border of the interconnection units around the semiconductor die. A third interconnect structure is formed over the semiconductor die perpendicular to the first interconnect structure. An insulating layer is formed over the semiconductor die and first interconnect structure.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: May 22, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Pandi C. Marimuthu, Il Kwon Shim, Yaojian Lin, Won Kyoung Choi
  • Patent number: 9978432
    Abstract: Apparatus, systems, and methods for write operations in spin transfer torque (STT) memory are described. In one embodiment, a memory comprises at least one spin-transfer torque (STT) memory device, temperature sensor proximate the STT memory device and a controller comprising logic, at least partially including hardware logic, to monitor an output of the temperature sensor, implement a first write operation protocol when the output of the temperature sensor fails to exceed a threshold temperature, and implement a second write operation protocol when the output of the temperature sensor exceeds the threshold temperature. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventor: Helia Naeimi
  • Patent number: 9978430
    Abstract: A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Sung Seo, Chul-Woo Park, Hong-Sun Hwang
  • Patent number: 9972379
    Abstract: First and second read requests are received. First data is fetched in response to the first read request. The fetched first data is then stored. The fetched first data corresponds to an address of the first read request. The fetched first data is returned in response to the second read request.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: May 15, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Gregg B. Lesartre
  • Patent number: 9966143
    Abstract: A solid state drive (SSD) with improved power efficiency includes one or more non-volatile memory devices configured to operate according to a programming voltage for a program function or an erase function and to a supply voltage for a read function. The SSD also includes a voltage regulator, external of the one or more non-volatile memory devices, having an output connected to the one or more non-volatile memory devices to supply the programming voltage and an input connected to receive a first voltage, the voltage regulator configured to convert the first voltage to the programming voltage. A discrete capacitor is connected to supply the first voltage to the voltage regulator. The one or more non-volatile memory devices operate according to the programming voltage supplied by the voltage regulator during both the normal operation of the SSD and in the event of a power loss or failure of the SSD.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: May 8, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Stephen K. Pardoe
  • Patent number: 9953700
    Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 24, 2018
    Assignee: SK Hynix Inc.
    Inventor: Bo-Kyeom Kim
  • Patent number: 9905307
    Abstract: Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: February 27, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Ashish Ghai, Lakshmi Kalpana Vakati, Ekamdeep Singh, Chang Siau, Gopinath Balakrishnan, Kapil Verma
  • Patent number: 9847119
    Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: December 19, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
  • Patent number: 9830963
    Abstract: Techniques are provided for reducing program disturb and short term data retention loss. Program disturb becomes worse for the drain-side memory cells at higher temperatures, while data retention generally does not become worse at higher temperatures. In one aspect, a deeper erase is provided for drain-side memory cells when the temperature is relatively high, to reduce program disturb. In another aspect, the verify levels of the programmed data states are lowered to reduce data retention loss when the temperature is relatively high. In another aspect, the number of read errors is used to adjust the depth of the depth of the erase operation. In another aspect, a pass voltage of a drain-side cell is lowered during a verify test for another cell to account for the deep erase of the drain-side cell.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: November 28, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Liang Pang, Vinh Diep, Ching-Huang Lu, Yingda Dong
  • Patent number: 9761285
    Abstract: Approaches for a circuit are provided. The circuit includes a sense amplifier circuit which includes a plurality of transistors enabled by a sense amplifier enable signal to output a first output data line true signal and a second output data line complement signal to a latching circuit, and the latching circuit which includes a primary driver actively driven by the first output data line true signal and a secondary driver actively driven by the second output data line complement signal such that the latching circuit outputs a read global data line.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: September 12, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Venkatraghavan Bringivijayaraghavan, Ramesh Raghavan
  • Patent number: 9691462
    Abstract: Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the pre-amplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell.
    Type: Grant
    Filed: September 27, 2014
    Date of Patent: June 27, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Seong-Ook Jung, Taehui Na, Byungkyu Song, Jung Pill Kim, Seung Hyuk Kang
  • Patent number: 9691495
    Abstract: A memory array with RAM and embedded ROM including multiple RAM cells, a ROM cell, and a ROM enable circuit. Each RAM cell has a RAM cell structure with a first and second power terminals and configured to operate as a RAM cell when the memory array is in a RAM mode. The ROM cell has the same RAM cell structure in which at least one transistor is modified to cause the ROM cell to have a predetermined logic state. The ROM enable circuit enables bit lines of the ROM cell to control supply voltages provided to the power terminals of the RAM cells so that they settle to predetermined logic states in a ROM mode. The modified transistor has a pseudo transistor structure having a modified substrate that operates as a resistance, such as a doping region in the substrate having the same polarity type as the substrate.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: June 27, 2017
    Assignee: NXP USA, INC.
    Inventors: Jianan Yang, Scott I. Remington, Shayan Zhang