Abstract: A semiconductor memory device is provided with a plurality of major memory cell blocks divided into sub-blocks and a redundant memory cell block identical in size with each sub-block. A row decoder circuit as well as two stages of column decoder circuits are provided in association with the major memory cell blocks. Write-in/sense amplifier circuits are located between the two stages of the column decoder circuits and a shifting circuit as well as between the redundant memory cell block and the shifting circuit, so that data bits are amplified after the selection and, then, one of the data bits is replaced with a redundant data bit, if necessary.

Abstract: An electrically programmable read only memory including an inhibiting circuit for preventing operation of the memory if a reading voltage higher than a predetermined level above a standard reading voltage is applied as a reading voltage during a read operation. The inhibiting circuit includes a detection circuit for providing a detection signal in the event that a reading voltage higher than the standard reading voltage is applied to the memory, and a logic circuit connected to an output of the detection circuit and having an output supplied as an inhibiting signal, for example, to inhibit a clock signal within the integrated circuit, upon reception of the detection signal. In a preferred embodiment, the detection circuit includes an enhanced-type transistor connected in series with a depleted transistor serving as a load. The enhanced transistor has a channel ranging between 50 and 100 microns and a channel length ranging from 4 to 6 microns.

Abstract: A semiconductor memory device comprises a memory cell array, a row decoder, a column decoder, a plurality of sense amplifiers, a plurality of write circuits, a signal switching circuit, a plurality of input buffers, a plurality of output buffers and a plurality of terminals, which are formed on the same chip. A switching signal B1/B4 is applied to one of the plurality of terminals. The semiconductor memory device has a 256K word by 4 bit organization when the switching signal B1/B4 is at an "L" level and has a 1M word by 1 bit organization when the switching signal B1/B4 is at an "H" level. The word organization can be switched mainly by the signal switching circuit.

Abstract: A dynamic semiconductor memory device is divided into a plurality of blocks. An operation of the semiconductor memory device is in either of a normal mode and a refresh mode, depending on the level of a refresh signal. In the normal mode, at an off time period, a potential on a bit line pair is equalized and a precharge potential is applied to the bit line pair. At the access time, equalizing of the potential on the bit line pair and supply of the precharge potential are stopped in a selected block and then, a word line driving signal is raised. On the other hand, in the refresh mode, at the off time period, the potential on the bit line pair is held at "H" and "L" levels by a sense amplifier, so that the potential on the bit line pair is not equalized and the precharge potential is not supplied. On this occasion, a precharge potential generating circuit is electrically disconnected from a power supply.

Abstract: A large scale integrable memory cell including a field effect transistor lying at a bit line and further including a storage capacitor which is formed by the wall of a trench and a cooperating electrode. The active region of the storage cell which lies outside the trench is fashioned in the form of a strip. The end face forms one part of the trench edge and the remaining portion of the trench edge is surrounded by a field oxide region.

Abstract: A serial access memory circuit provided with an improved serial addressing circuit which can be fabricated with a reduced number of elements, is disclosed. The memory circuit comprises a memory array of N columns to be serially accessed, and a serial selection circuit including a shift register of N/K stages, a control circuit generating K output signals and a gate circuit receiving output signals of N/K stages of the shift register and K output signals of the control circuit and generating N output signals.

Abstract: An amplifier (63) at the output (41) of a delay circuit (3) comprising capacitive memory elements (5, 7, 9, 11) which can be successively written and successively read in a manner which is delayed with respect to the writing sequence is formed as a differential amplifier having a special negative feedback (73, 75) and a double sampling circuit (55, 57) at its two inputs (61, 65) to obtain a sufficiently high output voltage and to serve as a hold circuit so that no stringent requirement need to be imposed on the bandwidth of the amplifier.

Abstract: A static random access memory cell implemented with metal Schottky field-effect transistors. The cell has first and second branches, each of the branches including: a depletion mode current limiting transistor having a drain connected to a first circuit node; a depletion mode load transistor having a drain connected to the source of the current limiting transistor and a source connected to a second circuit node; an enhancement mode active transistor having a drain connected to the second circuit node and a source connected to a third circuit node; an enhancement mode access transistor having a source connected to the second circuit node and a gate connected to the gate of the current limiting transistor; the gate of the load transistor connected to the second circuit node; the commonly connected gates of the current limiting transistor and the access transistor adapted to receive a word-line signal; and the drain of the access transistor adapted to receive a bit-line signal.

Abstract: A semiconductor memory device having a register and a memory cell array includes a controlling circuit for disconnecting an input/output circuit from a data bus and turning OFF a transfer gate provided between the register and data bus in a first operation mode and for connecting the input/output circuit to the data bus and turning ON the transfer gate in a second operation mode. In the first operation mode, a data read or write operation is performed between the memory cell array and an external circuit, and alternatively in the second operation mode the data read or write operation is performed between the register and the external circuit.

Abstract: Disclosed is a nonvolatile memory cell which utilizes a tunnel window to discharge the floating gate at a location spacially displaced from the program path for the cell. Also disclosed is a process for making such a memory cell.

Abstract: A storage device capable of being configured either as a single-access memory or as two separate memories is described. The storage device is especially suited for use in a digital signal processor performing numeric algorithms such as fast fourier transforms, autocorrelation and digital filtering because certain of such algorithms require fast dual access to two correlated, but separate, parameters while other such algorithms require fast single access to identical parameters. The storage device is shown in an exemplary embodiment empolying a multiplexer to affect writing of data from either of two data busses to one of the memories. In a second embodiment the write port of the memory is connected to one bus and the read port is connected to both busses. In this embodiment a dual-port address register file and a pair of address generation units provide indirect addressing capability for the storage device. Method of operating separate memories in a single-access or a dual-access mode is also described.

Abstract: This device is an all-optical digital architecture for carrying out compuions. Residue number system addition and multiplication tables are produced on an optically-addressable plane composed of optically bistable material. The plane of optically bistable material devices represents a residue number system addition or multiplication tables and is addressed by two intersecting signal beams from the top and a bias beam from the bottom. A combination of two signal beams exceeds the material transmission threshold in the intersection region letting bias light emerge as a position encoded signal beam.

Abstract: A semiconductor memory device which has a memory portion and a counter to count rows and/or columns of the memory portion, the counter being so constructed to return to a reset mode at the beginning of an address counting sequence when coming up to an arbitrary address such that an address or addresses corresponding to a region of the memory containing one or more defective memory cells and occurring after the arbitrary address are inaccessible. The counter thereby comprises a defective bit relief circuit built into the memory device.

Abstract: A Random Access Memory having a fast Clear operation includes a cell array (10) which has a plurality of memory cells arranged in rows and columns. Each of the rows is selected by word lines (12) and the data is output on column lines (14). Each of the word lines (12) is selected by a row decode circuit (20) or a Clear signal through OR gates (22). The Clear signal selects all of the word lines (12) such that each row in the cell array (10) is selected. The bit line associated with each column are pulled to ground through an N-channel transistor (36) and a bit line bar pulled high through a P-channel transistor (38). In addition, the V.sub.CC supply to the array (10) is decoupled from the memory cells by a P-channel transistor (40).

Abstract: A first-in first-out buffer memory with improved status flags to indicate not only memory empty and memory full conditions, but to further indicate conditions such as almost empty, almost full and half-full is disclosed. To generate the flags, counters continuously count the number of write and read operations, with a subtractor coupled thereto providing as an output the difference between the two counts. Time delay circuits initiated by write or read operations provide time delays sufficient to enable the counters and the subtractor to settle before clocking the result into a latch. The output of the latch is decoded, with a further time delay circuit clocking the decoder output thereinto to provide output signals for the foregoing status flags. The use of the time delay circuits and the clocking of status flags avoids any significant flag invalid time, making the flag signals constantly monitorable without regard to the timing of read and write operations.

Abstract: An optical recording medium which has data tracks and tracking lines juxtaposed with each other in a data recording region so as to write/read data into/from the data tracks, using the tracking lines as a reference. The data recording region is so configured as to have recessed portions and raised portions arranged alternatingly and extending along each other in a direction of data reading/writing. The so formed recessed portions and raised portions provide data tracks. With this configuration, the boundary edges between the respective recessed portions and the respective raised portions are used as tracking lines, so that data can be written in the recessed or raised portions, referring to the boundary edges as tracking lines.

Abstract: A self-synchronization device is disclosed for output circuits comprising a "3-state" gate of memories working in internal clock mode. This device consists of a sequential logic circuit which allows the "3-state" gate to go into low impedance only when a datum is available at the output of the read amplifiers.

Abstract: A drive timing signal generator for generating a drive timing signal used for driving transfer gate transistors in a memory device, is disclosed. The generator includes a boost circuit for operative generating a boosted voltage above the power voltage and an additional boost circuit for further boosting the boosted voltage generated by the boost circuit after the generation of the boosted voltage in a write mode.

Abstract: A static random access memory having a plurality of pairs of common data out lines. A plurality of bit line pairs are coupled to each pair of common data out lines. The common data out lines are automatically equalized at the end of each memory access cycle, and the accessed bit lines are automatically equalized at the end of each write cycle. Thus, the process of equalizing the common data out lines is removed from the critical timing path for accessing the memory, which eliminates one of the primary problems in the use of address transition detection in static memory devices.

Abstract: An improved First-In, First-Out data buffer and method of operation incorporates a plurality of arrays of random-access memory cells in column and row orientation per array in which all the cells in a row of one array are precharged simultaneously as memory cells are accessed for read or write operations in another array. Also, all the cells in a row of the other array may be precharged as the memory cells in the one array are accessed independently for read or write operations. Accesses to memory cells in addressed rows alternate from one array to another so that the signal conditioning of the memory cells in one array can take place before access in needed and while memory cells are being accessed in another array. Improved status logic unambigously designates the conditions of empty, half full and full, independent of the sequence of data read and write operations.