Abstract: A non-volatile semiconductor memory device, comprising: a non-volatile memory array, storing multi-values by setting a plurality of different threshold voltages for each memory cell, and a control circuit, controlling a write-in operation to the memory cell array. When data have been written into the memory cell, the control circuit selects an adjacent word line, uses an erasing level to perform write-in which is weaker than the data write-in, and verifies soft programming of the amount of one page, such that a narrow-banded erasing level distribution is realized in an adjacent memory cell.

Abstract: Exemplary methods, computer systems, and computer program products for fabricating key fields by a processor device in a computer environment are provided. In one embodiment, the computer environment is configured for, as an alternative to reading Count-Key-Data (CKD) data in order to change the key field, providing a hint to fabricate a new key field, thereby overwriting a previous key field and updating the CKD data.

Abstract: In one embodiment, a data migration technique enables a source storage system to efficiently and reliably migrate data to a destination storage system. The source storage system includes a copy engine that is configured to migrate or copy a set of data, e.g., one or more files, to the destination storage system using a file-based protocol over a network. The copy engine is also configured to ensure that any locks associated with the migrated data set are reclaimed at the destination storage system using a lock-based protocol. The source storage system further includes a proxy service that is configured to translate client requests to access the migrated data set to access requests executable (i.e., discernable) by the destination storage system. The proxy service then forwards or proxies the translated requests over the network to the destination storage system for processing.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors, and a non-volatile semiconductor memory (NVSM). A read frequency of a first logical block address (LBA) is maintained, and when the read frequency of the first LBA exceeds a threshold and a corresponding PBA is assigned to a data sector of the disk, first data stored in the data sector is copied to a memory segment of the NVSM. When the read frequency of the first LBA exceeds a threshold and the PBA is assigned to a memory segment of the NVSM, first data stored in the memory segment is copied to a data sector of the disk. When a read command is received to read the first LBA, a decision is made to read the first data from one of the NVSM and the disk.

Abstract: A method and other embodiments associated with solid-state drive command grouping are described. In one embodiment, a first command and a second command are grouped into a command pack, where the first command and the second command do not share a common channel for execution. A solid-state drive is controlled to execute the command pack on the solid-state drive, where executing the command pack causes the first command and the second command to execute concurrently on separate channels.

Abstract: The present invention is a protocol for maintaining cache consistency between multiprocessors within a tightly coupled system. A distributed directory is maintained within the data-sharing processors, so that copies can be invalidated when modified. All transfers are event driven, rather the polled, to reduce bus-bandwidth consumption. Deadlocks are avoided by placing to-be-executed command codes in the returned response packets, when the request-forwarding queues are full or not present.

Abstract: In a storage control apparatus, a first duplication control unit causes a logical volume in a disk array device to be copied to a secondary storage medium. A second duplication control unit causes the logical volume to be copied also to an export storage medium in a library device, in connection with the copying to the primary storage medium by the first duplication control unit, when export attributes indicate that the logical volume copied by the first duplication control unit is supposed to be exported. A medium ejection control unit causes the library device to eject the export storage medium, in response to an ejection request therefor.

Abstract: This specification discloses a method of managing data snapshot images in a storage system. The method includes the steps of: establishing a section allocation system that includes at least a media extent; establishing a section allocation table and a block association set in the media extent, wherein the section allocation table has a field containing information pointing to the block association set and the block association set corresponds to a Source Volume as the basis for performing a snapshot backup thereof; establishing a block association table in the block association set, wherein the block association table is used to store cross-reference information in order to correspond to backup data with the original storage addresses; and copying the data before updating the data into the section association set, when the data in the Source-Volume need to be updated.

Abstract: A first node includes a DMA engine for transferring data specified by a sequence of control blocks to a second node. When a control block does not require synchronization between memories, the DMA engine sends an end of transfer (EOT) message after the last datum, increments an EOT counter, and processes the next control block. When a control block requires synchronization and the EOT counter is at zero, the DMA engine sends an EOT with a flag after the last datum, increments the EOT counter, and waits for the EOT counter to return to zero before processing the next control block. A memory controller at the second node detects the EOT with or without a flag and generates an EOT acknowledgement with or without a flag. When a link interface at the second node detects the EOT acknowledgement with a flag, it sends an interrupt to a local processor complex.

Abstract: A dispatch mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. According to certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable that are to be processed by the co-processor. For instance, in certain embodiments, a designated portion of memory (e.g., “UCB”) is utilized, wherein a host processor may place information in such UCB and the co-processor can retrieve information from the UCB (and vice-versa). The UCB may thus be used to dispatch instructions of an executable for processing by the co-processor. In certain embodiments, the co-processor may comprise dynamically reconfigurable logic which enables the co-processor's instruction set to be dynamically changed, and the dispatching operation may identify one of a plurality of predefined instruction sets to be loaded onto the co-processor.

Abstract: A method, computer readable medium, and a system for communicating with networked clients and servers through a network device includes establishing a plurality of direct memory access (DMA) channels across a host system bus over which a plurality of executing applications each having a respective application driver communicate with a network through a network device configured to receive and transmit network data packets. At a first port in the network device, a first network data packet destined for an executing application is received. A first DMA channel over which to transmit the first network data packet towards the destined executing application is identified, and the first network data packet is transmitted to the destination executing application over the designated DMA channel mapping to the first port.

Abstract: A method, system and program product for executing a multi-function instruction in a computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: An apparatus for in-field configuration of a seismic device such as a seismic sensor may include a memory module having data for configuring the seismic device, a location sensor determining a location parameter for the seismic sensor, an alignment member aligning the location sensor with the seismic sensor, and a communication device transmitting the determined location parameter to a selected external device.

Abstract: In order to provide a system in which a single driver can totally control each periphery, there is provided a peripheral determination program executable on a main device installing the driver thereon. The peripheral determination program has a set of instructions including: acquiring device information assigned to each of a plurality of peripheral devices connected to the computer, the driver controlling operations of the plurality of peripheral devices, the device information indicating a model of each of the plurality of peripheral devices; extracting peripheral devices applicable to the driver out of the plurality of peripheral devices, the applicable peripheral devices being capable of executing all settings designated by the driver; selecting one peripheral device from the applicable peripheral devices; and determining the selected applicable peripheral device to be a terminal peripheral device.

Abstract: Communications connections with data storage systems are managed. A discovery process is executed to identify an iSCSI port on data storage system. Settings for the iSCSI port are accepted as user input at a server. Communication is performed from the server to the data storage system to configure the iSCSI port.

Abstract: A method of processing data comprising: processing a function using a processor operable to perform a plurality of functions, the processor having interrupts enabled; receiving an interrupt at the processor; suspending processing of the function; accessing at least one control parameter, the at least one control parameter indicating whether processing of the function should be resumed from the point where it was interrupted or whether the function should be repeated following the interrupt; following completion of the interrupt continuing processing of the function either at a start of the function or at a point at which it was interrupted dependent upon the control parameter. A function being an application, a thread, a system software routine, or multiple processing steps defined by software.

Abstract: A first free port present in a controller or a switch device is physically connected to a second free port present in a switch device (switch device in another storage device unit) other than the controller or switch device comprising the first free port. The possibility of logical connection via a physical path connecting the first free port and second free port is controlled.

Abstract: A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a memory FIFO (rmFIFO) region of a memory. A control unit implements logic to determine whether any prior received packet destined for that rmFIFO is still in a process of being stored in the associated memory by another DMA engine unit of the plurality, and prevent the one DMA engine unit from indicating completion of storing the current received packet in the reception memory FIFO (rmFIFO) until all prior received packets destined for that rmFIFO are completely stored by the other DMA engine units. Thus, there is provided non-locking support so that multiple packets destined for a single rmFIFO are transferred and stored in parallel to predetermined locations in a memory.

Abstract: Described are methods and systems that allow partial speculation (e.g., speculation within constraints). With partial speculation, after a fault is detected for example, speculation remains enabled for processor registers and other memories private to a microprocessor, while speculation normally permitted for certain other operations is suspended. Accordingly, while the fault is dispatched, some speculation is permitted as opposed to suspending all speculation. As such, microcode that makes use of speculation can be written.