Abstract: Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies.

Abstract: A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.

Abstract: In some embodiments, the invention involves a system and method relating to software caching with bounded-error delayed updates. Embodiments of the present invention describe a delayed-update software-controlled cache, which may be used to reduce memory access latencies and improve throughput for domain specific applications that are tolerant of errors caused by delayed updates of cached values. In at least one embodiment of the present invention, software caching may be implemented by using a compiler to automatically generate caching code in application programs that must access and/or update memory. Cache is accessed for a period of time, even if global data has been updated, to delay costly memory accesses. Other embodiments are described and claimed.

Abstract: A non-disruptive unassignment of an address from a fabric responsive to a request from a channel adapter. A logout command requests the fabric to unassign an address. The status of the address is thereby changed from active to unassigned and an acknowledgment sent back to the channel adapter.

Abstract: A method and apparatus are described for providing initialization in large storage systems as a background function, upon demand, and upon receipt of write requests. The initialization may be carried out under control of the hard disk drive itself, a storage controller, or both systems. The initialization is performed transparently to the host computer making operation of the storage system immediately after it is coupled to the host feasible.

Abstract: Disclosed is a method for selecting one of multiple proposed paths to a device. For each proposed path, a determination is made of a number of components the proposed path shares with existing paths to the device. The components comprise points of failure such that if one component fails then the path including the component fails. The determined number of shared components for each proposed path is used to select one proposed path.

Abstract: A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET instruction and a READ instruction. When a SET flag is retrieved for a given thread, the SET instruction sets a Bit flag in memory indicating that execution for the thread has been paused. The SET instruction is placed in the pipeline for execution. The following READ instruction for that thread, however, is prevented from entering the pipeline until, the SET instruction is executed and retired (resulting in a clearing of the Bit flag). Once the Bit flag has been cleared, the READ instruction is placed in the pipeline for execution. During the time that processing of one thread is paused, the execution of other threads may continue.

Abstract: A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern has an Opcode that defines what action to take when a particular data in the input data stream either matches or does not match the corresponding data being compared during a clock cycle. Each of the PUs communicate selected information so that PUs may be cascaded to enable longer patterns to be matched or to allow more patterns to be processed in parallel for a particular input data stream.

Abstract: According to some embodiments of the invention, a connector is provided for connecting any combination of an analog video source to either an analog display or a digital display or a digital video source to either an analog display or a digital display. Some preferred connectors have a serial differential digital interconnect that is pin/connector compatible with analog VGA or DB15. Some implementations of the invention provide a system and method for determining the inherent digital versus analog capability of a video source and a video display and configuring a connector according to the determination. Some implementations provide real-time display image quality assurance. Some embodiments provide a digital monitor with digital data streams having more than 8 bits per color, e.g., 10 bits or 12 bits per color.

Abstract: An information handling system having a plurality of modular servers and input-output (I/O) modules use virtual bridge switches to couple any of the plurality of modular servers to any of the I/O modules. This allows the modular servers to have the I/O connectivity dictated by the computing environment rather than having a fixed I/O assignment. The modular servers and I/O modules may be coupled together through serial I/O interfaces. Input and output buffers may be used to manage data flow traffic and multiplexers may be used to steer data to the appropriate input and output buffers. Control logic may be used to control the multiplexers and a programmable I/O mapping table may be used to describe which modular servers are coupled to which I/O modules.

Abstract: Systems and methods for improving the performance of a multimedia processor system by dynamically evaluating the current performance of the system and, if necessary, updating the configurations of the individual processors to improve the performance of the system. One embodiment comprises a method implemented in a multiprocessor system, including evaluating the performance of a current set of configuration objects installed on the processors, selecting a preferred set of configuration objects, and replacing one or more of the configuration objects in the current set to conform the current set to the preferred set. The method may evaluate the performance of configuration objects according to user preferences and may select preferred configuration objects according to a selectable strategy that can, for example, favor unification or diversity in the types of preferred configuration objects.

Abstract: Systems and methods for responding to a data transfer are disclosed. One embodiment comprises a method that includes the following steps: determining a sustainable data transfer rate for data transfers to/from an external memory medium, acquiring a data stream, transforming the data stream, and selecting a value for at least one operational parameter associated with acquiring or transforming the data stream in response to the sustainable data transfer rate.

Abstract: A multi-port apparatus used to communicably connect a computer and a plurality of apparatuses connected to the computer through the computer serial communication ports, such as two computer serial communication ports. A second serial communication port of the computer is connectable to ports corresponding to the plurality of apparatuses desired to be communicated with. A changeover switch is controlled through a first serial communication port of the computer to select one of the plurality of the apparatuses to connect with the second serial communication port of the computer and communicating with the one apparatus through the second serial communication port.

Abstract: A multi-protocol port interface coupled to a plurality of selectable circuits, each of the circuits being associated with an electrical interface standard and selectable via a mode-select input signal in order to facilitate communication with a peripheral device coupled to the port, the peripheral device having a circuit chosen from the plurality of selectable circuits and associated with an electrical interface standard.

Abstract: Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in a cache memory, un-fused, executed in parallel, and retired in order to optimized cost and performance.

Abstract: Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Hardware, in conjunction with compiler directives, allows memory write operations local to a CPU to occur in an arbitrary order, and places constraints on shared memory operation to occur in a specified order. Multiple sets of instructions are provided in which order of execution of the instructions is maintained through the use of CPU registers, write buffers in conjunction with assignment of sequence numbers to the instruction, or a hierarchical ordering system. The system ensures that an earlier designated instruction has reach a specified state of execution prior to a latter instruction reaching a specified state of execution. The ordering of operations allows memory operations local to a CPU to occur in conjunction with other memory operations that are not affected by such execution.

Abstract: For attached disk drive operations such a file copy and move, as well as more elaborate processes such as searching, virus-scanning and volume merge, a novel intelligent storage engine concept is disclosed. In one embodiment, a storage engine (40), utilizing local processor intelligence, and accessed through a suitable driver (60) and API (App. B), carries out disk access operations without burdening the host CPU (22) and without imposing data traffic on the local CPU bus (34), except for returning results data in an appropriate case.

Abstract: A system for write forwarding in a storage environment employing distributed virtualization includes a first and a second storage server providing access to a first and a second physical storage device, respectively, a virtual device server and a virtual device client. The virtual device server may be configured to aggregate storage in the first and second physical storage device into a virtual storage device and make the virtual storage device accessible to the virtual device client for I/O operations. An update requested by the virtual device client may require a first physical write operation at the first physical storage device and a second physical write operation at the second physical device. The virtual device client may be configured to send an update request to the first storage server, rather than to both the first and the second storage servers.

Abstract: A method is provided for efficiently managing the connection of processor modules and input/output interface modules at a drastically reduced cost. A management server searches IFT and ST tables after receiving an instruction from the system management server to connect an input/output interface module to a processor, creates a condition list requested by the input/output interface module, and selects an input/output interface matching the condition list JL from an unassigned input/output interface module management table UNT. The management server next instructs the input/output interface switch to connect the processor with the selected input/output interface. The management server instructs the input/output device management server and the network management server to setup a connection utilizing the selected input/output interface, and rewrites the tables UNT and SPT.

Abstract: Systems for servicing the data and memory requirements of system devices. A DMA engine that includes a data reservoir is provided that manages and arbitrates the data requests from the system devices. An arbitration unit is provided that only allows eligible devices to make a data request in any given cycle to ensure that all devices will be serviced within a programmable time period. The data reservoir contains the data buffers for each channel of each device. A memory interface ensures that sufficient data for each channel is present in the data reservoir by making requests to a system's memory based on an analysis of each channel. Based on this analysis, a request is either made to the system's main memory, or the channel waits until it is evaluated again in the future. Each channel is thereby guaranteed a response time.