Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract: A hypervisor acquires an I/O command that has been issued from a virtual computer. The hypervisor judges whether or not a target of an I/O that complies with the I/O command is an unassigned port associated device that is a device associated with an I/O port that is coupled to an I/O controller that is not assigned to a virtual computer that is an issuing source of the I/O command. In the case in which the result of the judgment is positive, the hypervisor does no execute an I/O to the unassigned port associated device, and returns a virtual execution result to the virtual computer that is an issuing source of the I/O command.

Abstract: Apparatus, system and methods are provided for performing speculative data prefetching in a chip multiprocessor (CMP). Data is prefetched by a helper thread that runs on one core of the CMP while a main program runs concurrently on another core of the CMP. Data prefetched by the helper thread is provided to the helper core. For one embodiment, the data prefetched by the helper thread is pushed to the main core. It may or may not be provided to the helper core as well. A push of prefetched data to the main core may occur during a broadcast of the data to all cores of an affinity group. For at least one other embodiment, the data prefetched by a helper thread is provided, upon request from the main core, to the main core from the helper core's local cache.

Abstract: A universal serial bus (USB) device communicates with a USB host over a USB to remotely wake up the USB host over the USB when the USB host is in a low power (e.g. deep sleep) mode. The USB device performs an activity to wake up the USB host. The USB host performs a remote wake up process in response to detecting the activity by the USB device. The USB host performs a resume process in response to performing the remote wake up process by the USB host. The USB device wakes up in response to the USB host performing the resume process.

Abstract: A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

Abstract: In one implementation, a pipeline processor is provided having a base architecture that includes one or more decoders operable to decode program instructions and generate one or more decoded instructions, and one or more execution units operable to execute the one or more decoded instructions. Each execution unit includes one or more execution pipeline stages. The pipeline processor architecture further includes one or more additional co-processor pipelines. The one or more decoders of the base architecture are operable to recognize one or more instructions to be processed by a given co-processor pipeline and pass the one or more recognized instructions to the given co-processor pipeline for decoding and execution.

Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.

Abstract: One embodiment is directed to a method of segregating one or more content addressable storage systems into a plurality of virtual pools. The virtual pools can be allocated to different content sources and/or can be assigned to different storage system capabilities. Another embodiment is directed to transmitting with an input/output request for a content unit information specifying at least one storage capability to be applied to the content unit, and/or receiving such an I/O and implementing the specified storage system capabilities. Another embodiment is directed to extracting from an I/O request from a source information relating to an impact of the I/O on at least one characteristic of the content units stored on a CAS system from the source.

Abstract: Provided is a unit for protecting data with respect to data transfer between memories of a disk controller. The disk controller for controlling data transfer between a host computer and a disk drive includes: a channel unit having a channel memory; a cache unit having a cache memory, and a control unit for controlling the data transfer. The data transferred to/from the host computer is transferred in a packet between the channel memory and the cache memory, and The control unit for verifying consistency of information included in a header of the packet to be transferred to decide whether transfer can be permitted when the packet is transferred.

Abstract: A priority determining method and apparatus can reduce a total waiting time of DMA request blocks by granting priority to each of Direct Memory Access (DMA) request blocks transmitting a DMA request signal, based on Data Transfer Amounts (DTAs) of the DMA request blocks and Arrival Times (ATs) of the DMA request signals, counting the number of priority changes of each of DMA request blocks whose priority is changed in the priority granting process, and if a DMA request signal is received from a new DMA request block, determining priorities of the DMA request blocks based on the counted the number of priority changes.

Abstract: A method for performing virtualization, includes managing data between a virtual machine and a bus controller by transmitting an input output (IO) request from the virtual machine to a service virtual machine that owns the bus controller. According to an alternate embodiment, the method for performing virtualization includes managing isochronous data between a virtual machine and a bus controller. Other embodiments are described and claimed.

Abstract: A method for issuing shadow requests to manage bandwidth allocation between an application that issues input/output (I/O) operation requests and an I/O device. A bandwidth manager detects the completion of an I/O operation, which includes either a read operation or a write operation. The bandwidth manager calculates a statistical duration for future I/O operations between the application and the I/O device based on throughput statistics related to past I/O operations. The bandwidth manager generates a shadow request for reserving a position in a queue that stores pending I/O requests for the I/O device for a first future I/O operation request from the application and having a duration related to the statistical duration, and inserts the shadow request into the queue. Advantageously, applications that do not make frequent I/O operation requests in advance may still execute I/O operations because bandwidth is reserved for future I/O operation requests via the shadow requests.

Abstract: An interface circuit and method for programming or communicating with an integrated circuit (IC) via a power supply pin is provided herein. In general, the power supply pin may be coupled for receiving a relatively constant voltage signal during a first mode of operation (i.e., a normal mode) and a modulated voltage signal during a second mode of operation (i.e., a programming or communication mode). The interface circuit may be coupled between the power supply pin and other IC components for decoding the modulated voltage signal into data. Various encoding/decoding schemes may be used by the interface circuit and method for communicating data to the IC over the power supply lines. The decoded data may be used for programming or communication purposes.

Abstract: The present invention uses a smart control module with HID descriptors to communicate with the host side in accordance with the standard HID communication protocol, so as to interact with the smart card, which can eliminate the need of installing a private driver from a particular manufacturer when installing its reader/writer. The driver of the HID device can be installed automatically upon installation of the operating system. The users can use the reader/writer easily without carrying a driver around. It is not necessary for the users to deal with upgraded versions of the driver, to consider compatibilities of drivers for different products, to confront usage risks of the operating system due to the driver, or to worry about contamination of the operating system resulted from the installation and uninstallation of the driver.

Abstract: Provided is a memory controller configured to control a flash memory device. The memory controller includes: a buffer memory configured to store data to be written in the flash memory device; a buffer memory interface configured to control read and write operations of the buffer memory; and an automatic command processing unit configured to interpret a data command generated by a host hardware device.

Abstract: Versatile serial bus connectivity is provided for enabling detection and use of passive media output devices that connect to a host device through a serial bus connector. In addition, serial bus connectivity is extended to video output devices that can use analog video data.

Abstract: A method, apparatus, and computer program product for processing a chain linked transport control channel program in an I/O processing system is provided. The method includes receiving a first command message at a control unit specifying a first predetermined sequence number for performing a first set of one or more commands as part of an I/O operation. The method further includes receiving a second command message specifying a second predetermined sequence number for performing a second set of one or more commands as part of the I/O operation. The method also includes comparing the sequence numbers to a next expected predetermined sequence number to determine an order of performing the commands. The method additionally includes executing the commands in the determined order to perform the I/O operation.

Abstract: Embodiments of the present invention address deficiencies of the art in respect to threading model switching between asynchronous I/O and synchronous I/O models and provide a novel and non-obvious method, system and computer program product for autonomic threading model switching based upon I/O request types. In one embodiment, a method for autonomic threading model switching based upon I/O request types can be provided. The method can include selectably activating and de-activating a blocking I/O threading model according to a volume of received and completed blocking I/O requests.

Abstract: An amplifier (unit) linked via a daisy type serial bus sends a transmission start signal SC and then sends the local data DATAn. If data from an amplifier at the downstream side is not received before transmission of the local data DATAn is completed, the delimit of the data from each amplifier is changed by adding an idle time data TIDD.

Abstract: A low-latency queue pair (QP) is provided for I/O Adapters that eliminates the overhead associated with work queue elements (WQEs) and defines the mechanisms necessary to allow the placement of the message directly on the queue pair.