Abstract: Some embodiments include apparatuses and methods having a memory cell string that can include memory cells located in different levels of the apparatus. The memory cell string can include a body associated with the memory cells. At least one of such embodiments can include a module configured to apply a negative voltage to at least a portion of the body of the memory cell string during an operation of the apparatus. The operation can include a read operation, a write operation, or an erase operation. Other embodiments are described.

Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.

Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.

Abstract: It is aimed to detect an error of an address abnormality in a memory. An address error detection information generating unit generates address error detection information for detecting an error relating to an access address for a memory. A control part stores the address error detection information generated by the address error detection information generating unit in the memory at a time of write access. An error detecting part compares the address error detection information generated by the address error detection information generating unit with the address error detection information stored in the memory to detect an error at a time of read access.

Abstract: A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.

Abstract: Command/address (CA) pads of a wafer may be coupled with one or more logic circuits of the wafer to support transmission of a test signal between different memory dies of the wafer. A CA pad of a first memory die may be coupled with a repeater circuit in a scribe region of the wafer, and the repeater circuit may be coupled with a corresponding control circuit in the scribe region. These circuits may support repetition of a signal from a probe card to one or more other CA conductive paths of one or more other memory dies of the wafer. The repeater circuit may receive a test signal from the CA pad, which may be coupled with and receive the test signal from the probe card, and may transmit the test signal to another CA pad of another memory die based on a configuration of the control circuit.

Abstract: A semiconductor memory device according to an embodiment includes a string, a bit line, a well line, and a sequencer. The string includes first and second select transistors, and memory cell transistors using a ferroelectric material. The bit line and the well line are connected to the first and second select transistors, respectively. At a time in an erase verify operation, the sequencer is configured to apply a first voltage to the memory cell transistors, to apply a second voltage lower than the first voltage to the first select transistor, to apply a third voltage lower than the first voltage to the second select transistor, to apply a fourth voltage to the bit line, and to apply a fifth voltage higher than the fourth voltage to the well line.

Abstract: A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.

Abstract: A semiconductor circuit includes a first circuit that applies an inverted voltage of a voltage at a first node to a second node, a second circuit that applies an inverted voltage of a voltage at the second node to the first node, a first transistor that couples the first node to a third node, and a first memory element having a first terminal coupled to the third node and a second terminal to which a control voltage is to be applied. The semiconductor circuit further includes a second transistor having a drain coupled to the third node and a gate coupled to one of the first node or the second node, a third transistor having a drain coupled to the third node and a gate coupled to the other of the first node or the second node, and a driver.

Abstract: A semiconductor memory device includes: a first wiring and a second wiring; a first selection transistor, a memory transistor, and a second selection transistor connected between the first wiring and the second wiring; and a third wiring and a fourth wiring connected to gate electrodes of the first selection transistor and the second selection transistor. From a first timing to a second timing, a first voltage that turns the first selection transistor ON is supplied to the third wiring, and a second voltage that turns the second selection transistor OFF is supplied to the fourth wiring. From the second timing to a third timing, a third voltage that turns the first selection transistor OFF is supplied to the third wiring, and at a fourth timing between the first timing and the third timing, at least one of a voltage and a current of the first wiring is detected.

Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

Abstract: A ternary processing cell used as a memory cell and capable of in-memory arithmetic is disclosed which includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first ternary operand, a ternary input establishing a second ternary operand, and a ternary output, wherein the ternary output represents a multiplication of the first ternary operand and the second ternary operand.

Abstract: Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

Abstract: A semiconductor memory device operated under control of a controller. The semiconductor memory device including a control logic and a data input/output circuit. The control logic configured to store logic data and generate a plurality of pieces of circular data based on the logic data in response to an output command of the logic data that is received from the controller. The data input/output circuit configured to select circular data corresponding to a set warm-up cycle among the plurality of pieces of circular data and output the selected circular data to the controller.

Abstract: Described herein are apparatuses, methods, and systems associated with a memory circuit in a three-dimensional (3D) integrated circuit (IC). A control circuit of the memory circuit may include logic transistors in a logic layer of the 3D IC. The control circuit may further include one or more interconnects (e.g., local or global interconnects) and/or other devices in one or more front-side metal layers of the 3D IC. The memory circuit may further include a memory array in back-side metal layers of the 3D IC. The memory array may be formed in the back-side metal layers that are closest to the logic layer. Other embodiments may be described and claimed.

Abstract: A voltage generation circuit includes a driver configured to generate an internal voltage by driving an external voltage depending on a driving signal; an amplifier configured to generate the driving signal depending on a result of comparing a reference voltage and a feedback voltage; and a switch configured to delay a decrease of the internal voltage by precharging a node of the amplifier with a predetermined voltage depending on a control signal.

Abstract: Apparatuses and methods related to a memory system including a controller and an array of memory cells are provided. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.

Abstract: A memory device includes a bay comprises a plurality of word lines, a plurality of bit lines, and a memory cell connected to a first word line of the plurality of word lines and a first bit line of the plurality of bit lines, a row decoder configured to bias at least one word line of the word lines adjacent to the first word line and float remaining non-adjacent word lines of the plurality of word lines not adjacent to the first word line, in an access operation associated with the memory cell, and a column decoder configured to bias at least one bit line of the bit lines adjacent to the first bit line and float remaining non-adjacent bit lines of the plurality of bit lines not adjacent to the first bit line, in the access operation.

Abstract: A memory device includes a plurality of memory cells, each memory cell including a switching element and a data storage element having a phase change material, and each memory cell connected to one of a plurality of wordlines and to one of a plurality of bitlines, a decoder circuit configured to determine at least one of the plurality of memory cells as a selected memory cell, and a programming circuit configured to input a program current to the selected memory cell to perform a program operation, to detect a holding voltage of the selected memory cell, and to adjust a magnitude of the program current based on the detected holding voltage. The selected memory cell is turned off when a voltage across the selected memory cell is lower than the holding voltage.