Patents Examined by Alfredo Bermudez Lozada
  • Patent number: 10347348
    Abstract: The invention provides a semiconductor memory device capable of setting input data correctly, including: an input circuit outputting input data to a data bus; a logic circuit outputting the input data on the data bus to digit lines selected by a column address in response to a writing clock signal synchronized with an external clock signal; a page buffer holding data of the digit lines in holding circuits of a column selected by the column address in response to an inner clock signal generated by delaying the writing clock signal, and an address counter generating the column address in response to the writing clock signal. The column address is supplied to the logic circuit in response to the writing clock signal, and the column address is supplied to the page buffer in response to the inner clock signal which has been delayed.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 9, 2019
    Assignee: Winbond Electronics Corp.
    Inventor: Hidemitsu Kojima
  • Patent number: 10338831
    Abstract: Present disclosure includes a system for preserving data in a volatile memory and a method thereof. The volatile memory comprises a plurality of refreshing units, and each of the refreshing units comprises a plurality of word lines for storing data. The system comprises an accessing unit. The accessing unit is configured to detect a row-hammer indication indicating a first word line is frequently accessed, wherein the accessing unit is configured to copy data stored in the first word line to a second word line when the row-hammer indication is detected on the first word line, wherein the data stored in the first and the second word lines are available to be selectively accessed.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 2, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Patent number: 10338146
    Abstract: In order to create a control observer for any battery type in a structured and at least partially automated manner, first, a nonlinear model of the battery, in form of a local model network including a number of local, linear, time-invariant, and dynamic models, which each have validity in specific ranges of the input variables, is determined from the measuring data of a previously ascertained, optimized experimental design via a data-based modeling method. For each local model (LMi) of the model network determined in this manner, a local observer is then determined. The control observer (13) for estimating the SoC then results from a linear combination of the local observers.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: July 2, 2019
    Assignee: AVL List GmbH
    Inventors: Christoph Hametner, Stefan Jakubek, Amra Suljanovic
  • Patent number: 10337930
    Abstract: A number of variations may include a method which may include determining a temperature rise in an IGBT junction without the use of a temperature estimation or measurement device because determination may be made by first determining the power loss due to the conduction losses of the IGBT and power loss associated with switching the IGBT where these losses may be determined by utilizing the saturation voltage of the IGBT, IGBT PWM duty cycle, IGBT switching frequency, fundamental frequency along with a lookup table for the switching energies and the phase current going through the IGBT. The determined power loss may be multiplied by a measured, sensed or obtained thermal impedance from the IGBT junction. Finally, the determined temperature rise of the IGBT junction may be added to a measured, sensed or obtained temperature of the coolant in order to determine the absolute temperature of the IGBT junction.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: July 2, 2019
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: S. M. Nayeem Hasan, Bryan M. Ludwig, David P. Tasky
  • Patent number: 10332605
    Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
  • Patent number: 10325664
    Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: June 18, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada
  • Patent number: 10319422
    Abstract: A decoder according to one embodiment of the invention includes a set of lines, a resonator circuit, a set of input leads for receiving input signals, and a set of switches for coupling some of the lines within the set of lines to the resonator circuit in response to the input signals while the other lines within the set of lines are at a first binary voltage. The lines are coupled to a set of pointer circuits. The pointer circuits perform logic functions on the signals on the lines when the resonating signal is at a second binary voltage opposite the first binary voltage to thereby decode the input signals. Because the lines are driven high and low by a resonator circuit, the decoder circuit power consumption is less than it would be if the lines were pulled up and down by a set of pullup and pulldown transistors.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: June 11, 2019
    Inventor: David A. Huffman
  • Patent number: 10319431
    Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
  • Patent number: 10312248
    Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: June 4, 2019
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
  • Patent number: 10297292
    Abstract: A sense structure may include sense amplifiers each having measuring and reference terminals for receiving a measuring and a reference current, respectively, output circuitry for providing an output voltage based upon the measuring and reference currents, and voltage regulating circuitry in cascade configuration for regulating a voltage at the measuring and reference terminals. The regulating circuitry may include measuring and regulating transistors and a reference regulating transistor having a first conduction terminal coupled with the measuring terminal and with the reference terminal, respectively, a second conduction terminal coupled with the output circuitry and a control terminal coupled with a biasing terminal. Biasing circuitry is for providing a biasing voltage to the biasing terminal, and common regulating circuitry is for regulating the biasing voltage. Each sense amplifier may also include local regulating circuitry for regulating the biasing voltage applied to the biasing terminal.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: May 21, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonino Conte, Mario Micciche', Santi Nunzio Antonino Pagano
  • Patent number: 10283181
    Abstract: Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: May 7, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: David J. Toops
  • Patent number: 10276227
    Abstract: A method for verifying a write operation in a memory cell (e.g., a non-volatile memory cell) that includes performing a first read operation of the memory cell to measure a first current associated with the memory cell and comparing the measured first current associated with the memory cell to a first predetermined threshold current to determine whether the write operation changed the state of the memory cell. If the measured first current associated with the memory cell indicates the write operation did change the state of the memory cell the method further includes performing a second read operation of the memory cell to measure a second current associated with the memory cell and comparing the measured second current associated with the memory cell to a second predetermined threshold current to determine whether the write operation changed the state of the memory cell to the desired state or an intermediate state.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yu-Der Chih, Chien-Ye Lee, Jenn-Jou Wu, Yi-Chieh Chiu, Yi-Chun Shih, William J. Gallagher
  • Patent number: 10276222
    Abstract: In accordance with one embodiment, a method for accessing a memory is provided, including carrying out a first access to the memory and charging, for a memory cell, a bit line coupled to the memory cell to a value which is stored or to be stored in the memory cell, holding the state of the bit line until a second access, which follows the first access, and outputting the held state if the second access is a read access to the memory cell.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: April 30, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Kuenemund, Gerd Dirscherl, Gunther Fenzl, Joel Hatsch, Nikolai Sefzik
  • Patent number: 10275178
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a first variable resistance element, a first switching element coupled to the first variable resistance element via a first line, a second variable resistance element, and a second switching element coupled to the second variable resistance element via a second line, wherein a distance between the first switching element and the first variable resistance element is larger than a distance between the second switching element and the second variable resistance element, and wherein a second path from a first terminal of the second switching element to the second variable resistance element includes a resistance component, a resistance of the second path being greater than a resistance of a first path, the first path being from a first terminal of the first switching element to the first variable resistance element.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: April 30, 2019
    Assignee: SK HYNIX INC.
    Inventor: Nam-Kyun Park
  • Patent number: 10249371
    Abstract: A control circuit that controls a memory including a storage region and a redundant region, the control circuit includes a detector that detects a defective block in the memory, and a controller that switches, when the detector has detected the defective block, a data storage scheme of the first block detected as the defective block from a first storage scheme to a second storage scheme in which the number of bits of data to be stored in each of memory elements is smaller than the number of bits of data to be stored in each of the memory elements in the first storage scheme, and that stores a portion of data stored in the first block in the first storage scheme to be stored in the first block in the second storage scheme.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 2, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Masazumi Maeda
  • Patent number: 10242743
    Abstract: A method of storing information or data in a nonvolatile memory device with multiple-page programming. The method, in one aspect, is able to activate a first drain select gate (“DSG”) signal. After loading the first data from a bit line (“BL”) to a nonvolatile memory page of a first memory block in response to activation of the first DSG signal during a first clock cycle, the first DSG signal is deactivated. Upon activating a second DSG signal, the second data is loaded from the BL to a nonvolatile memory page of a second memory block. The first data and the second data are simultaneously written to the first memory block and the second memory block, respectively.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: March 26, 2019
    Assignee: NEO Semiconductor, Inc.
    Inventor: Fu-Chang Hsu
  • Patent number: 10217518
    Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. The drain-end select gate transistors of unselected sub-blocks are made temporarily conductive for a time period during the ramp up of the unselected word line voltages to reduce the amount of capacitive coupling up of the respective memory string channel. This reduces a channel gradient which can exist in the memory string channels, thereby also reducing the read disturb. Further, the time period is greater when the selected word line is in a source-end or midrange subset of the word lines than when the selected word line is in a drain-end subset of the word lines. Another option involves omitting the injection disturb countermeasure, or providing a less severe injection disturb countermeasure, when the unselected sub-blocks are unprogrammed.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: February 26, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Hong-Yan Chen, Yingda Dong
  • Patent number: 10217510
    Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
  • Patent number: 10210937
    Abstract: A semiconductor device includes a memory array including a plurality of memory blocks. Each memory block includes a pipe transistor, a drain select transistor and a first memory cell connected between the pipe transistor and a bit line, and a source select transistor and a second memory cell connected between the pipe transistor and a common source line. The semiconductor device further includes an operation circuit configured to apply an operating voltage to a memory block selected to perform program and read operations, and a gate control circuit configured to control a gate of the pipe transistor included in an unselected memory block.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: February 19, 2019
    Assignee: SK hynix Inc.
    Inventor: Jin Su Park
  • Patent number: 10204689
    Abstract: Non-volatile storage systems and method of operating non-volatile storage systems are disclosed. A crept up voltage on a memory cell control gate adjacent to a select gate is prevented, reduced, and/or discharged. In some aspects, the crept up voltage is not allowed to happen on the memory cell next to the select gate after a sensing operation. In some aspects, the voltage may creep up on the memory cell control gate after a sensing operation, but it is discharged. Reducing and/or preventing the crept up voltage may reduce the electric field between the dummy memory cell and select gate transistor. This may prevent, or at least reduce, changes in threshold voltage of the select gate transistor. Additional problems may also be solved by a reduction of the crept up voltage on the dummy memory cell control gates.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: February 12, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Ching-Huang Lu, Anubhav Khandelwal, Changyuan Chen, Cynthia Hsu, Yingda Dong