Patents Examined by Alfredo Bermudez Lozada
  • Patent number: 11004501
    Abstract: A memory device comprises a memory cell array with memory cells arranged in a cell string coupled to a metal bit line, a sense amplifier for providing a sensing current to the memory cell array, and a memory controller for controlling the sense amplifier to provide the sensing current to access data during a memory access cycle. The memory controller performs operations comprising: during a pre-charging stage of the memory access cycle, providing a pre-charging voltage to the sense amplifier to drive the sense amplifier such that a particular voltage is provided to the memory cell array; during a first sensing stage, providing the pre-charging voltage to the sense amplifier; and during a second sensing stage, providing a sensing voltage to drive the sense amplifier such that the particular voltage provided to the memory cell array is maintained.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 11, 2021
    Assignee: Macronix International Co., Ltd.
    Inventor: Chung-Kuang Chen
  • Patent number: 10998014
    Abstract: A memory device configured to support multiple memory densities is provided. The memory device includes a first plurality of electrical contacts corresponding to a first command/address channel, a second plurality of electrical contacts corresponding to a second command/address channel, a third plurality of electrical contacts corresponding to a first data bus, a fourth plurality of electrical contacts corresponding to a second data bus, and mode selection circuitry configured to place the memory device in the first mode or the second mode. In the first mode, the first plurality of memory cells is operatively coupled to the first and third pluralities of electrical contacts and the second plurality of memory cells is operatively coupled to the second and fourth plurality of electrical contacts. In the second mode, the first and second pluralities of memory cells are both operatively coupled to the first and third pluralities of electrical contacts.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Martin Brox
  • Patent number: 10998040
    Abstract: A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 4, 2021
    Assignee: GSI TECHNOLOGY, INC.
    Inventors: Lee-Lean Shu, Eli Ehrman
  • Patent number: 10991422
    Abstract: High-efficiency control technology for non-volatile memory. A non-volatile memory has single level cells (SLCs) and multiple level cells (e.g., MLCs or TLCs) and is controlled by a controller. According to the controller at the device end, a host allocates a system memory to provide a host memory buffer (HMB). The controller at the device end uses the HMB to buffer write data issued by the host, and then flushes the write data from the HMB to multi-level cells of the non-volatile memory without passing single level cells of the non-volatile memory to reduce write amplification problems due to the frequent use of the single-level cells.
    Type: Grant
    Filed: July 28, 2019
    Date of Patent: April 27, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Chien-Ting Huang, Liang-Cheng Chen
  • Patent number: 10978159
    Abstract: Adaptive write operations for non-volatile memories select programming parameters according to monitored programming performance of individual memory cells. In one embodiment of the invention, programming voltage for a memory cell increases by an amount that depends on the time required to reach a predetermined voltage and then a jump in the programming voltage is added to the programming voltage required to reach the next predetermined voltage. The adaptive programming method is applied to the gate voltage of memory cells; alternatively, it can be applied to the drain voltage of memory cells along a common word line. A circuit combines the function of a program switch and drain voltage regulator, allowing independent control of drain voltage of selected memory cells for parallel and adaptive programming. Verify and adaptive read operations use variable word line voltages to provide optimal biasing of memory and reference cells during sensing.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sau Ching Wong
  • Patent number: 10971216
    Abstract: A random-access memory cell includes first and second voltage supply nodes, first and second complementary output nodes, first and second complementary bit lines associated with the memory cell, and a word line associated with the memory cell. Pairs of series-connected cross-coupled p-channel and n-channel hybrid FinFET transistors are connected between the voltage supply nodes, the first bit line coupled to the first output node, and the second bit line coupled to the second output node.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: April 6, 2021
    Assignee: Microsemi SoC Corp.
    Inventors: Jonathan W. Greene, John McCollum
  • Patent number: 10957391
    Abstract: An array organization and architecture for a content addressable memory (CAM) system. More specifically, a circuit is provided for that includes a first portion of the CAM configured to perform a first inequality operation implemented between 1 to n CAM entries. The circuit further includes a second portion of the CAM configured to perform a second inequality operation implemented between the 1 to n CAM entries. The first portion and the second portion are triangularly arranged side by side such that the first inequality operation and the second inequality operation are implemented between the 1 to n CAM entries using the same n wordlines.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John E. Barth, Jr., Dean L. Lewis
  • Patent number: 10957406
    Abstract: According to some embodiments, a memory system includes a memory device including a plurality of memory cells capable of storing a plurality of bit data corresponding to a plurality of levels, respectively, and a controller configured to read data from the memory device, perform an error correction when there is an error in the read data, and determine a variation in a level before and after error correction of the read data.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: March 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yichao Lu
  • Patent number: 10949934
    Abstract: A power managing method includes receiving a scan command for a load apparatus connected to a multi-tap type energy measuring apparatus. Further, the power managing method includes determining a power consumption pattern of the load apparatus for a predetermined time based on a signal corresponding to the scan command from the user terminal. Further, the power managing method includes receiving information of the load apparatus. Further, the power managing method includes registering the load apparatus based on the determined power consumption pattern and the information of the load apparatus received from the user terminal.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: March 16, 2021
    Assignee: Encored Technologies, Inc.
    Inventors: Jong-Woong Choe, Dae Young Kim
  • Patent number: 10950312
    Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
  • Patent number: 10916304
    Abstract: A semiconductor storage device includes first, second, and third wiring layers, each including a plurality of first wirings, fourth and fifth wiring layers, each including a plurality of second wirings, wherein the fourth wiring layer is between the first and second wiring layers and the fifth wiring layer is between the second and third wiring layers, memory cells formed at intersections of the first and second wirings of adjacent wiring layers, first and second contacts electrically connected to a first wiring of the first wiring layer and a first wiring of the second wiring layer, respectively, in the hook-up region, a sixth wiring layer including a first connection wiring electrically connected to the first contact and a second connection wiring electrically connected to the second contact and separated from the first connection wiring, and first and second drive circuits electrically connected to the first and second connection wirings, respectively.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: February 9, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroyuki Hara
  • Patent number: 10902923
    Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 26, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada
  • Patent number: 10891076
    Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array (having a plurality of bit line sections) provides a mechanism to logically combine the computation results across multiple bit line sections in a section and across multiple sections, and transmit the combined result as an output of the processing array and/or store the combined result into one or more of those multiple bit line sections.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: January 12, 2021
    Assignee: GSI Technology, Inc.
    Inventors: Bob Haig, Eli Ehrman, Dan Ilan, Patrick Chuang, Chao-Hung Chang, Mu-Hsiang Huang
  • Patent number: 10892024
    Abstract: A variety of applications can include systems and/or methods of optimizing results from scanning a memory device, where the memory device has stacked multiple reliability specifications. Information about a block of multiple blocks of a memory device can be logged, where the information is associated with a combination of reliability specifications. A refresh of the block can be triggered based on exceeding a threshold condition for the combination of reliability specifications.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Ankit Vashi, Harish Reddy Singidi, Kishore Kumar Muchherla
  • Patent number: 10885981
    Abstract: A cell of a content-addressable memory (CAM) has a first switch, a second switch and a storage unit. A first end of the first switch and a first end of the second switch are coupled to a matchline. The first switch is controlled by a first search signal, and the second switch is controlled by a second search signal. The second search signal is complementary to the first search signal. The storage unit has a first inverter and a second inverter. The first inverter has a first latch node coupled to a second end of the first switch. The second inverter is cross-coupled to the first inverter and has a second latch node coupled to a second end of the second switch.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: January 5, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zih-Yu Chiu, Hsin-Wen Chen, Yen-Yao Wang
  • Patent number: 10886003
    Abstract: A semiconductor memory device includes a switching controller, a voltage generator and control logic. The switching controller is connected to a local word line. The voltage generator, connected to the switching controller, is configured to generate an operating voltage according to an input clock signal and transfer the operating voltage to the switching controller. The control logic is configured to control operations of the voltage generator and the switching controller. The control logic is configured to detect an amount of leakage current of the local word line by counting a number of pulses of the input clock signal.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: January 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Jae Ho Lee
  • Patent number: 10878898
    Abstract: A memory system includes a first memory, a second memory, and a first circuit. The first memory includes a memory cell array including memory cell transistors, and a peripheral circuit configured to read data of a plurality of bits stored in a memory cell transistor of the memory cell array based on a comparison between threshold voltages of the memory cell transistor and at least a part of n determination voltages (n?3). The first circuit is configured to calculate an estimated value of each of n?m determination voltages based on values of m determination voltages (2?m?n?1) among the n determination voltages, and calculate a difference between a value of each of the n?m determination voltages and a corresponding estimated value. The second memory is configured to store values of the m determination voltages and the difference for each of the n?m determination voltages.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryo Sekiguchi, Shingo Yanagawa, Yasuhiko Kurosawa, Eriko Akaihata
  • Patent number: 10872900
    Abstract: An example semiconductor device includes: n conductive layers including first to nth conductive layers stacked in a first direction; a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type closer to the nth conductive layer than the first semiconductor region; a semiconductor layer provided between the first semiconductor region and the second semiconductor region, extending in the first direction, penetrating the n conductive layers, and having an impurity concentration lower than a first conductive impurity concentration of the first region and a second conductive impurity concentration of the second region; n charge storage regions including first to nth charge storage regions provided between the n conductive layers and the semiconductor layer, and a control circuit that controls a voltage applied to the n conductive layers to always prevent charges from being stored in at least one of the n charge storage regions.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: December 22, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoya Sanuki, Yusuke Higashi, Hideto Horii, Masaki Kondo, Hiroki Tokuhira, Hideaki Aochi
  • Patent number: 10861573
    Abstract: Apparatuses and methods related to a memory system including a controller and an array of memory cells. An example apparatus can include a controller configured to receive operational characteristics of an array of memory cells based on prior operations performed by the array of memory cells, determine a set of trim settings for the array of memory cells based on the operational characteristics of the array of memory cells, wherein the set of trim settings are associated with desired operational characteristics for the array of memory cells, and send the set of trim settings to the array of memory cells.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Aswin Thiruvengadam, Daniel L. Lowrance, Peter Feeley
  • Patent number: 10860320
    Abstract: A device and method for facilitating orthogonal data transposition during data transfers to/from a processing array and a storage memory since the data words processed by the processing array (using computational memory cells) are stored orthogonally to how the data words are stored in storage memory. Thus, when data words are transferred between storage memory and the processing array, a mechanism orthogonally transposes the data words.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: December 8, 2020
    Assignee: GSI Technology, Inc.
    Inventors: Bob Haig, Patrick Chuang, Chih Tseng, Mu-Hsiang Huang