Abstract: Each memory block in the flash memory is added with corresponding information bit(s) that store(s) information indicating whether erasure of the memory block has been completed before power-off. This allows easily finding out which memory block in the flash memory is undergoing an erase operation at the time of power-off. When the flash memory is powered on again, the information in the corresponding information bit(s) of the memory blocks may be read out and checked to determine whether there is any memory block of which the erasure had not been completed before the last power-off. If so, the memory blocks in the flash memory will be reprogrammed during the re-powering. This can avoid possible failure in reading data from some memory cells in the flash memory.

Abstract: A circuit of cells used as a memory array and capable of in-memory arithmetic which includes a plurality of signed ternary processing, each signed ternary processing cell includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first signed ternary operand, a signed ternary input forming a second signed ternary operand, and a signed ternary output, wherein the signed ternary output represents a signed multiplication of the first signed ternary operand and the second signed ternary operand, a sense circuit adapted to output a subtraction result.

Abstract: Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another.

Abstract: A clock-generating circuit is provided, which includes a voltage-reference circuit, a tracking-voltage-generating circuit, a voltage regulator, an oscillation generator, and a level shifter. The voltage-reference circuit and the tracking-voltage-generating circuit respectively convert the external voltage into a reference voltage and a temporary reference voltage. The voltage regulator receives the reference voltage and the temporary reference voltage, and it converts the reference voltage or the temporary reference voltage into an oscillation power-supply voltage. The oscillation generator generates a first clock signal according to the oscillation power-supply voltage. The level shifter converts a voltage amplitude of the first clock signal to generate a second clock signal that is output by the clock-generating circuit.

Abstract: Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit may perform a program operation on selected memory cells coupled to a selected word line among the plurality of memory cells. The control logic may control the program operation of the peripheral circuit. The program operation may include a plurality of program loops. Each of the program loops may include a program phase and a verify phase. The verify phase may include one or more verify operations. The control logic may be further configured to count a number of the verify operations performed by the peripheral circuit in the verify phase included in one of the plurality of program loops during the program operation.

Abstract: Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: The present disclosure relates to a logic operation circuit for computation in memory, which comprises an equivalent circuit input terminal, a reference circuit input terminal, a reset input terminal and an output terminal; wherein the equivalent circuit input terminal is configured to input the equivalent voltage of a memory computing array, the reset input terminal is configured to input a reset voltage, and the reference circuit input terminal is configured to input a reference voltage; the logic operation circuit for computation in memory outputs different output voltages according to the difference between the equivalent voltage and the reference voltage, and the output voltage is output through the output terminal; the logic operation circuit of the present disclosure has a simple structure, reduced complexity and effectively saved resources.

Abstract: Various implementations described herein are related to a device having memory circuitry activated by a power-gated supply. The device may include level shifting circuitry that receives a switch control signal in a first voltage domain, shifts the switch control signal in the first voltage domain to a second voltage domain, and provides the switch control signal in the second voltage domain. The device may include power-gating circuitry activated by the switch control signal in the second voltage domain, and the power-gating circuitry may provide the power-gated supply to the memory circuitry to trigger activation of the memory circuitry with the power-gated supply when activated by the switch control signal in the second voltage domain.

Abstract: An ionic redox transistor comprises a solid channel, a solid reservoir layer, and a solid electrolyte layer disposed between the channel and the reservoir layer. The channel exhibits a substantially linear current-voltage relationship in a first range of voltages, and a nonlinear current-voltage relationship in a second range of voltages that is greater than the first range of voltages. One or both of the substantially linear current-voltage relationship or the nonlinear current-voltage relationship of the channel is varied by changing the concentration of ions such as oxygen vacancies in the channel. Ion or vacancy transport between the channel and the reservoir layer across the electrolyte layer occurs in response to applying a voltage between the channel and the reservoir layer. Subject to the first range of voltages, the channel can function as a synapse device. Subject to the second range of voltages, the channel can function as a neuron device.

Abstract: In an embodiment, an apparatus is disclosed that includes a power management integrated circuit (PMIC). The PMIC includes a voltage regulator supplied by a first power source and configured to generate a first output and a charge pump supplied by a second power source and configured to generate a second output. A bias voltage output of the power management integrated circuit is generated based at least in part on the first output and the second output. The charge pump is configured to adjust the second output based at least in part on a comparison between the bias voltage output and a reference voltage.

Abstract: Apparatuses and techniques are described for reducing the number of latches used in sense circuits for a memory device. The number of internal user data latches in a sense circuit is reduced by using an external data transfer latch to store a bit of user data, in place of an internal user data latch. The user data in the data transfer latches identifies a subset of the data states which are not prohibited from having a verify test. The subset is shifted as the program operation proceeds, at specified program loops, to encompass higher data states. The completion of programming by a memory cell is indicated by the user data latches and another internal latch of the sense circuit in place of the external data transfer latch.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including initiating a read operation with respect to a block of the memory device, selecting, based on a set of criteria, a default read offset from a set of read offsets, wherein the set of criteria includes at least one of: a parameter related to trigger rate, or an amount of time that an open block is allowed to remain open to control threshold voltage shift due to storage charge loss, and applying the default read offset to a read operation performed with respect to the block.

Abstract: According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit.

Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.

Abstract: A phase detection circuit may include an edge trigger circuit, a strobe generation circuit and a phase detector. The edge trigger circuit generates a falling clock signal and a rising clock signal based on a reference clock signal and a target clock signal. The strobe generation circuit generates a falling strobe signal and a rising strobe signal having pulse widths varying based on a phase relationship between the reference clock signal and the target clock signal. The phase detector generates a phase detection signal based on the falling clock signal, the rising clock signal, the falling strobe signal and the rising strobe signal.

Abstract: The present disclosure relates to a shiftable memory comprising: a plurality of memory cells arranged in rows and columns, wherein the memory cells of the rows are interconnected, thereby forming chains of memory cells; at least one first serial output data port; output data logic for connecting an output of any of the chains of memory cells to the first serial output data port, or at least one first parallel output data port and at least one read shift register configured for serially collecting serial output data from the output of any of the chains of memory cells; and/or at least one first serial input data port; input data logic for connecting the first serial input data port to an input of any of the chains of memory cells, or at least one parallel input data port and at least one write shift register for serially shifting input data to the input of any of the chains of memory cells; and a controller configured to control the shifting of the data in the chains of memory cells, the controller further con

Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). Data are stored to and retrieved from a group of memory cells in the NVM using a controller circuit. The data are retrieved using a first set of read voltages which are applied to the respective memory cells. The first set of read voltages are accumulated into a history distribution, which is evaluated to arrive at a second set of read voltages based upon characteristics of the history distribution. A calibration operation is performed on the memory cells using the second set of read voltages as a starting point. A final, third set of read voltages is obtained during the calibration operation to provide error rate performance at an acceptable level. The third set of read voltages are thereafter used for subsequent read operations.

Abstract: A memory device includes a magnetic tunnel junction (MTJ) pillar between a top electrode and a bottom electrode. An amorphous dielectric hardmask is in contact with a first portion of an uppermost surface of the MTJ pillar. A first portion of a metal layer is disposed on opposite sidewalls of the amorphous dielectric hardmask and in contact with a second portion of the uppermost surface of the MTJ pillar extending outwards from the amorphous dielectric hardmask for providing the top electrode. A dielectric underlayer is in contact with a first portion of a bottommost surface of the MTJ pillar, while a second portion of the metal layer is disposed on opposite sidewalls of the dielectric underlayer. The second portion of the metal layer is in contact with a second portion of the bottommost surface of the MTJ pillar extending outwards from the dielectric underlayer for providing the bottom electrode.