Patents Examined by Alfredo Bermudez Lozada
  • Memory device system-on-chip including the same and method of operating the same
    Patent number: 10847208
    Abstract: A memory device includes a memory cell array and a peripheral circuit. The memory cell array receives a first power supply voltage and includes a plurality of bit cells that store data based on the first power supply voltage. The peripheral circuit is receives a second power supply voltage and controls the memory cell array based on the second power supply voltage. The peripheral circuit includes a voltage generation circuit that receives the first power supply voltage and the second power supply voltage. The voltage generation circuit adaptively adjusts a word-line driving voltage directly or indirectly based on a difference between the first power supply voltage and the second power supply voltage during a memory operation on the plurality of bit cells, and applies the word-line driving voltage to a first word-line coupled to first bit cells selected from the bit cells.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: In-Hak Lee, Sang-Yeop Baeck, Jae-Seung Choi
  • Write data processing circuits and methods associated with computational memory cells
    Patent number: 10847213
    Abstract: A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 24, 2020
    Assignee: GSI Technology, Inc.
    Inventors: Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
  • Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers
    Patent number: 10847212
    Abstract: A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability for selected write data in a bit line section to be logically combined (e.g. logically ANDed) with the read result on a read bit line, as if the write data were the read data output of another computational memory cell being read during the read operation. When accumulation logic is implemented in the bit line sections, the implementation and utilization of additional read logic circuitry provides a mechanism for selected write data in a bit line section to be used as the data with which the read result on the read bit line accumulates, before the newly accumulated result is captured and stored in the bit line section's read register.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: November 24, 2020
    Assignee: GSI Technology, Inc.
    Inventors: Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
  • Memory devices and methods of controlling an auto-refresh operation of the memory devices
    Patent number: 10832755
    Abstract: A memory device includes a memory medium and a memory controller. The memory medium has a memory cell array and may be configured to generate a self-refresh signal, which varies based on an internal temperature of the memory medium, to control a self-refresh operation performed on the memory cell array. The memory controller may be configured to calculate an auto refresh cycle of an auto refresh control signal for controlling an auto-refresh operation of the memory medium based on the self-refresh signal.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: November 10, 2020
    Assignee: SK hynix Inc.
    Inventors: Youngjae Jin, Jin Wook Kim
  • Memory cell state in a valley between adjacent data states
    Patent number: 10811090
    Abstract: A memory cell can have a state in a valley between adjacent data states. A determination can be made whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. A signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley can be transmitted.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak, Robert B. Eisenhuth
  • Semiconductor memory device and erase verify operation
    Patent number: 10803965
    Abstract: A semiconductor memory device according to an embodiment includes a string, a bit line, a well line, and a sequencer. The string includes first and second select transistors, and memory cell transistors using a ferroelectric material. The bit line and the well line are connected to the first and second select transistors, respectively. At a time in an erase verify operation, the sequencer is configured to apply a first voltage to the memory cell transistors, to apply a second voltage lower than the first voltage to the first select transistor, to apply a third voltage lower than the first voltage to the second select transistor, to apply a fourth voltage to the bit line, and to apply a fifth voltage higher than the fourth voltage to the well line.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Takashi Maeda
  • Tunable negative bitline write assist and boost attenuation circuit
    Patent number: 10783956
    Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
  • Tunable negative bitline write assist and boost attenuation circuit
    Patent number: 10783958
    Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinesh Chandra, Eswararao Potladhurthi, Dhani Reddy Sreenivasula Reddy, Krishnan S. Rengarajan
  • Resistive memory storage apparatus and writing method thereof including disturbance voltage
    Patent number: 10783962
    Abstract: A writing method of a resistive memory storage apparatus includes: applying one of a set voltage and a reset voltage serving as a first selected voltage to a memory cell and obtaining a first read current; applying a disturbance voltage to the memory cell and obtaining a second read current; and determining whether a relationship between the first and second read currents satisfies a preset relationship, and if not, applying the other of the set voltage and the reset voltage serving as a second selected voltage to the memory cell and applying the first selected voltage to the memory cell again. A polarity of the disturbance voltage is different from that of the first selected voltage, and the absolute value of the disturbance voltage is less than that of the second selected voltage. A resistive memory storage apparatus is also provided.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: September 22, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Lih-Wei Lin, Lung-Chi Cheng, Min-Yen Liu, Huan-Ming Chiang
  • Secure semiconductor chip and operating method thereof
    Patent number: 10778679
    Abstract: A semiconductor chip comprises at least one data bus to transmit data processed by the semiconductor chip, an electric potential generator block packaged together with the at least one data bus to be blocked from external light by a package, the electric potential generator block to detect an event in which the package is unable to block the external light, and a switch configured to block a transmission of at least some data in the at least one data bus if the event is detected. A semiconductor chip comprises an energy harvesting element inside a package. The energy harvesting element may comprise an on-chip photodiode. A depackaging attack causes the generation of a voltage of a photodiode, and thus a change in physical state of the packaging can be detected.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: September 15, 2020
    Assignee: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
    Inventors: Hyoung Ho Ko, Byong Deok Choi
  • Three-dimensional (3-D) write assist scheme for memory cells
    Patent number: 10777244
    Abstract: An integrated circuit includes an array of write assist circuits electrically connected to a memory cell array. Each write assist circuit is configured to set an operating voltage of a corresponding memory cell. Each write assist circuit is configured to receive at least a first control signal, and generate an output signal at least in response to the first control signal. The output signal controlling the operating voltage of the corresponding memory cell. Each write assist circuit includes a programmable voltage tuner. The programmable voltage tuner includes a first P-type transistor and a second P-type transistor coupled to the first P-type transistor. A first terminal of the first P-type transistor is configured as a first input node to receive a first select control signal. A first terminal of the second P-type transistor is configured as a second input node to receive a second select control signal.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chieh Chiu, Chia-En Huang, Fu-An Wu, I-Han Huang, Jung-Ping Yang
  • Read data processing circuits and methods associated memory cells
    Patent number: 10777262
    Abstract: A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: September 15, 2020
    Assignee: GSI Technology, Inc.
    Inventors: Bob Haig, Eli Ehrman, Chao-Hung Chang, Mu-Hsiang Huang
  • Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line
    Patent number: 10770152
    Abstract: Methods of operating a memory device include comparing input data to data stored in strings of series-connected memory cells coupled to a data line, generating a respective resistance in series with each string of series-connected memory cells while comparing the plurality of digits of input data to the stored data, comparing a representation of a level of current in the data line to a reference, deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than the reference, and deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kenneth J. Eldredge, Frankie F. Roohparvar, Luca De Santis, Tommaso Vali
  • Nonvolatile memory comprising variable resistance transistors and method for operating the same
    Patent number: 10756267
    Abstract: A first memory unit includes a first bipolar-variable-resistance and a first control transistor. This first memory unit is configured to provide a function of a flash memory with first bipolar-variable-resistance transistor serving as a storage. In addition, a second bipolar-variable-resistance transistor and a second control transistor with the same structure as first memory unit can be used to serve as a second memory unit. An isolation transistor is connected between the first memory unit and the second memory unit. The isolation transistor can electrically isolate the first memory unit and the second memory unit from each other, thereby preventing sneak current from flowing between arrays among memory circuits.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 25, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Steve S. Chung, E-Ray Hsieh
  • SLC page read
    Patent number: 10755793
    Abstract: NAND memory devices are described that utilize higher read-margin cell types to provide a more granular read disturb indicator without utilizing dummy cells. For example, a NAND architecture may have some cells that are configured as SLC or MLC cells. SLC or MLC cells have more read disturb margin—that is these cells can withstand more read disturb current leakage into the cell before a bit error occurs than TLC or QLC cells. These higher margin cells may serve as the read disturb indicator for a group of cells that have a comparatively lower read disturb margin. Since there are more pages of these higher margin cells than there are pages of dummy cells, these indicators may serve a smaller group of pages than the dummy pages. This reduces the time needed to complete a read disturb scan as fewer pages need to be scanned.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Harish Singidi, Scott Stoller, Jung Sheng Hoei, Ashutosh Malshe, Gianni Stephen Alsasua, Kishore Kumar Muchherla
  • Monitoring battery health of a battery used in a device
    Patent number: 10753982
    Abstract: Approaches provide for determining an internal rate of resistance of a battery in a computing device. In particular, various examples enable using a processor to expose the battery to a first load at a first rate of consumption and to measure a first analog voltage across the battery during exposure of the battery to the first load. The processor is able to expose the battery to a second load a second rate of consumption and to measure a second analog voltage across the battery during exposure of the battery to the second load. Linear equations can be used to solve for the battery's internal rate of resistance based at least in part on the first rate of consumption, the first analog voltage, the second rate of consumption, and the second analog voltage. In various embodiments, the battery's internal rate of resistance can be correlated to a battery health indicator.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: August 25, 2020
    Assignee: Square, Inc.
    Inventor: Jeremy Wade
  • Memory block select circuitry including voltage bootstrapping control
    Patent number: 10748620
    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Semiconductor devices
    Patent number: 10748590
    Abstract: A semiconductor device may include a power supply circuit, a word line control circuit, and a memory circuit. The power supply circuit may drive a pre-charge voltage to a level of an external voltage based on a write initialization signal which is enabled if a command has a predetermined level combination. The word line control circuit may generates two or more word line selection signals that are sequentially counted based on the write initialization signal. The memory circuit may sequentially select a plurality of word lines based on the word line selection signals. The memory circuit may drive bit lines of memory cells connected to the selected word line to the pre-charge voltage. The memory circuit may store data, which are loaded on the bit lines to have a level of the pre-charge voltage, into the memory cells connected to the selected word line.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: August 18, 2020
    Assignee: SK hynix Inc.
    Inventor: Kibong Koo
  • Global wordline decoder and semiconductor device having the same
    Patent number: 10741248
    Abstract: A global word line decoder may include a voltage switching unit and a plane switching unit. The voltage switching unit may decode a plurality of operating voltages to output a selected voltage and an unselected voltage, and the plane switching unit may receive the selected voltage and the unselected voltage, and decode the selected voltage and the unselected voltage to output decoded voltages to a global word line coupled to a selected plane, among a plurality of planes. The selected voltage may include a first pre-decoded voltage and a second pre-decoded voltage, and the plane switching unit may swap and output the first pre-decoded voltage and the second pre-decoded voltage according to a position of a selected word line.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Moon Soo Sung
  • Static random access memory with write assist circuit
    Patent number: 10734066
    Abstract: A write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Chih-Yu Lin, Sahil Preet Singh, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao