Patents Examined by Alfredo Bermudez Lozada
  • Testing circuitry and methods for analog neural memory in artificial neural network
    Patent number: 11393546
    Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: July 19, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly, Steven Lemke, Nha Nguyen, Vipin Tiwari, Nhan Do
  • Memory device with switching element connected in series to resistance change memory element
    Patent number: 11386944
    Abstract: According to one embodiment, a memory device includes first and second wiring lines, a memory cell connected between the first and second wiring lines and including a resistance change memory element and a switching element connected in series to the resistance change memory element, and a determination circuit determining a determination object resistance state set in advance to the resistance change memory element based on a determination object voltage applied to the second wiring line when the switching element makes a transition from an on-state to an off-state.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: July 12, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Kosuke Hatsuda
  • Memory device and method for operating the same including setting a recovery voltage
    Patent number: 11386954
    Abstract: A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: July 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Marco Sforzin, Paolo Amato, Innocenzo Tortorelli
  • Virtual ground non-volatile memory array
    Patent number: 11380698
    Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: July 5, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Hung Quoc Nguyen, Nhan Do
  • Memory system for performing a read operation and an operating method thereof
    Patent number: 11373709
    Abstract: A memory system includes a memory device including a plane including a plurality of memory blocks, each memory block including a plurality of memory cells, each memory cell capable of storing multi-bit data, and a controller configured to determine that a second memory block is a candidate block when an issue-triggering operation is performed for a first memory block, adjust levels of read voltages when receiving a read command for data stored in the second memory block determined as the candidate block, and control the memory device to supply adjusted levels of the read voltages to the second memory block to perform a read operation corresponding to the read command. The second memory block and the first memory block are included in the same plane. The issue-triggering operation includes either a program operation or an erase operation.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: June 28, 2022
    Assignee: SK hynix Inc.
    Inventor: Dae Sung Kim
  • Apparatuses and methods using negative voltages in part of memory write, read, and erase operations
    Patent number: 11367486
    Abstract: Some embodiments include apparatuses and methods having a memory cell string that can include memory cells located in different levels of the apparatus. The memory cell string can include a body associated with the memory cells. At least one of such embodiments can include a module configured to apply a negative voltage to at least a portion of the body of the memory cell string during an operation of the apparatus. The operation can include a read operation, a write operation, or an erase operation. Other embodiments are described.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Koji Sakui
  • Multi-bit memory system with adaptive read voltage controller
    Patent number: 11367489
    Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: June 21, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tsukasa Tokutomi, Masanobu Shirakawa, Marie Takada
  • Self-referencing memory device
    Patent number: 11355174
    Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Riccardo Muzzetto
  • Destruction of data and verification of data destruction on a memory device
    Patent number: 11348650
    Abstract: A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Scott Anthony Stoller, Kevin R Brandt, Qisong Lin
  • Storage control circuit, storage apparatus, imaging apparatus, and storage control method
    Patent number: 11348657
    Abstract: It is aimed to detect an error of an address abnormality in a memory. An address error detection information generating unit generates address error detection information for detecting an error relating to an access address for a memory. A control part stores the address error detection information generated by the address error detection information generating unit in the memory at a time of write access. An error detecting part compares the address error detection information generated by the address error detection information generating unit with the address error detection information stored in the memory to detect an error at a time of read access.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: May 31, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masaki Murozuka
  • Interconnected command/address resources
    Patent number: 11342042
    Abstract: Command/address (CA) pads of a wafer may be coupled with one or more logic circuits of the wafer to support transmission of a test signal between different memory dies of the wafer. A CA pad of a first memory die may be coupled with a repeater circuit in a scribe region of the wafer, and the repeater circuit may be coupled with a corresponding control circuit in the scribe region. These circuits may support repetition of a signal from a probe card to one or more other CA conductive paths of one or more other memory dies of the wafer. The repeater circuit may receive a test signal from the CA pad, which may be coupled with and receive the test signal from the probe card, and may transmit the test signal to another CA pad of another memory die based on a configuration of the control circuit.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Jason M. Johnson, Yoshinori Fujiwara, Kevin G. Werhane
  • Single-rail memory circuit with row-specific voltage supply lines and boost circuits
    Patent number: 11322200
    Abstract: A single-rail memory circuit includes an array of memory cells arranged in rows and columns and peripheral circuitry connected to the array for facilitating read and write operations with respect to selected memory cells. The peripheral circuitry includes, but is not limited to, boost circuits for the rows. Each boost circuit is connected to a wordline for a row and to a discrete voltage supply line for the same row. Each boost circuit for a row is configured to increase the voltage levels on the wordline and the voltage supply line for the row during a read of any selected memory cell within the row. Increasing the voltage levels on the wordline and on the voltage supply line during the read operation effectively boosts the read current. A method of operating the memory circuit reduces the probability of a read fail.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 3, 2022
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Vivek Raj, Shivraj G. Dharne, Uttam K. Saha, Mahbub Rashed
  • Semiconductor memory device and erase verify operation
    Patent number: 11322212
    Abstract: A semiconductor memory device according to an embodiment includes a string, a bit line, a well line, and a sequencer. The string includes first and second select transistors, and memory cell transistors using a ferroelectric material. The bit line and the well line are connected to the first and second select transistors, respectively. At a time in an erase verify operation, the sequencer is configured to apply a first voltage to the memory cell transistors, to apply a second voltage lower than the first voltage to the first select transistor, to apply a third voltage lower than the first voltage to the second select transistor, to apply a fourth voltage to the bit line, and to apply a fifth voltage higher than the fourth voltage to the well line.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: May 3, 2022
    Assignee: Kioxia Corporation
    Inventor: Takashi Maeda
  • Semiconductor circuit and semiconductor circuit system to suppress disturbance in the semiconductor circuit
    Patent number: 11309025
    Abstract: A semiconductor circuit includes a first circuit that applies an inverted voltage of a voltage at a first node to a second node, a second circuit that applies an inverted voltage of a voltage at the second node to the first node, a first transistor that couples the first node to a third node, and a first memory element having a first terminal coupled to the third node and a second terminal to which a control voltage is to be applied. The semiconductor circuit further includes a second transistor having a drain coupled to the third node and a gate coupled to one of the first node or the second node, a third transistor having a drain coupled to the third node and a gate coupled to the other of the first node or the second node, and a driver.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: April 19, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yusuke Shuto
  • Semiconductor memory device, memory system, and defect detection method
    Patent number: 11309394
    Abstract: A semiconductor memory device includes: a first wiring and a second wiring; a first selection transistor, a memory transistor, and a second selection transistor connected between the first wiring and the second wiring; and a third wiring and a fourth wiring connected to gate electrodes of the first selection transistor and the second selection transistor. From a first timing to a second timing, a first voltage that turns the first selection transistor ON is supplied to the third wiring, and a second voltage that turns the second selection transistor OFF is supplied to the fourth wiring. From the second timing to a third timing, a third voltage that turns the first selection transistor OFF is supplied to the third wiring, and at a fourth timing between the first timing and the third timing, at least one of a voltage and a current of the first wiring is detected.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: April 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Shinya Haraguchi
  • Memory block select circuitry including voltage bootstrapping control
    Patent number: 11302397
    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: April 12, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Memory devices and memory operational methods
    Patent number: 11295812
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Ternary in-memory accelerator
    Patent number: 11281429
    Abstract: A ternary processing cell used as a memory cell and capable of in-memory arithmetic is disclosed which includes a first memory cell, adapted to hold a first digital value, a second memory cell, adapted to hold a second digital value, wherein a binary combination of the first digital value and the second digital value establishes a first ternary operand, a ternary input establishing a second ternary operand, and a ternary output, wherein the ternary output represents a multiplication of the first ternary operand and the second ternary operand.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: March 22, 2022
    Assignee: Purdue Research Foundation
    Inventors: Shubham Jain, Anand Raghunathan, Sumeet Kumar Gupta
  • Memory arrays, ferroelectric transistors, and methods of reading and writing relative to memory cells of memory arrays
    Patent number: 11276449
    Abstract: Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container having a first inner surface. Metal-containing material is configured as a second container nested within said first container. The second container has a second inner surface with an area less than the first inner surface. Ferroelectric material is configured as a third container nested within the second container. The third container has a third inner surface with an area less than the second inner surface. Gate material is within the third container. Some embodiments include memory arrays having ferroelectric transistors as memory cells. Some embodiments include methods of writing/reading relative to memory cells of memory arrays when the memory cells are metal-ferroelectric-metal-insulator-semiconductor (MFMIS) transistors.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Durai Vishak Nirmal Ramaswamy, Wayne Kinney
  • Semiconductor memory device configured to output data based on a warm-up cycle and operating method thereof
    Patent number: 11270744
    Abstract: A semiconductor memory device operated under control of a controller. The semiconductor memory device including a control logic and a data input/output circuit. The control logic configured to store logic data and generate a plurality of pieces of circular data based on the logic data in response to an output command of the logic data that is received from the controller. The data input/output circuit configured to select circular data corresponding to a set warm-up cycle among the plurality of pieces of circular data and output the selected circular data to the controller.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Ja Yoon Goo, Sung Hwa Ok